Expand description
Device Control Register
Structs§
- DcrSpec
- Device Control Register
Type Aliases§
- CshminR
- Field
CSHMINreader - Minimum CS high deselect time. 0 - one cycle, 1 - two cycles, etc. - CshminW
- Field
CSHMINwriter - Minimum CS high deselect time. 0 - one cycle, 1 - two cycles, etc. - CslmaxR
- Field
CSLMAXreader - Maximum CS low active time. 0 - no limit, n - (n+1) cycles - CslmaxW
- Field
CSLMAXwriter - Maximum CS low active time. 0 - no limit, n - (n+1) cycles - CslminR
- Field
CSLMINreader - Minimum CS low active time. N - (n+1) cycles - CslminW
- Field
CSLMINwriter - Minimum CS low active time. N - (n+1) cycles - DqseR
- Field
DQSEreader - DQS enable. Setting to 1 indicates device provides DQS signal for Rx data latching - DqseW
- Field
DQSEwriter - DQS enable. Setting to 1 indicates device provides DQS signal for Rx data latching - FixlatR
- Field
FIXLATreader - Indicate PSRAM is fixed latency or variable latency - FixlatW
- Field
FIXLATwriter - Indicate PSRAM is fixed latency or variable latency - HyperR
- Field
HYPERreader - HyperBus protocol - HyperW
- Field
HYPERwriter - HyperBus protocol - R
- Register
DCRreader - RbsizeR
- Field
RBSIZEreader - Row boundary size. 0 - no row boundary, n - row boundary at 2^(n+3) bytes - RbsizeW
- Field
RBSIZEwriter - Row boundary size. 0 - no row boundary, n - row boundary at 2^(n+3) bytes - TrcminR
- Field
TRCMINreader - Write/Read cycle minimum time - TrcminW
- Field
TRCMINwriter - Write/Read cycle minimum time - W
- Register
DCRwriter - XlegacyR
- Field
XLEGACYreader - Xccela legacy protocol - XlegacyW
- Field
XLEGACYwriter - Xccela legacy protocol