Struct CacheHierarchyInfo 

pub struct CacheHierarchyInfo {
    pub l1_size_kb: usize,
    pub l2_size_kb: usize,
    pub l3_size_kb: usize,
    pub cache_line_size: usize,
    pub l1_latency: usize,
    pub l2_latency: usize,
    pub l3_latency: usize,
    pub memory_latency: usize,
    pub prefetch_distance: usize,
}

Cache hierarchy information

Fields

l1_size_kb: usize

L1 cache size per core (KB)

l2_size_kb: usize

L2 cache size per core (KB)

l3_size_kb: usize

L3 cache size shared (KB)

cache_line_size: usize

Cache line size (bytes)

l1_latency: usize

L1 latency (cycles)

l2_latency: usize

L2 latency (cycles)

l3_latency: usize

L3 latency (cycles)

memory_latency: usize

Memory latency (cycles)

prefetch_distance: usize

Prefetch distance

Implementations

impl CacheHierarchyInfo

pub fn detect() -> Self

Detect the CPU cache hierarchy.

On Linux the cache sizes and line size are read from /sys/devices/system/cpu/cpu0/cache/index*/. Access latencies (in cycles) are not exposed by the kernel, so they are populated with conservative, clearly-documented typical values rather than fabricated per-machine measurements.

If sysfs cannot be read the returned values fall back to the same documented typical defaults.

Trait Implementations

impl Debug for CacheHierarchyInfo

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.