Struct Netlist 

pub struct Netlist<I>
where
    I: Instantiable,
{ /* private fields */ }

A netlist data structure

Implementations

impl<I> Netlist<I>

where I: Instantiable,

pub fn new(name: String) -> Rc<Self>

Creates a new netlist with the given name

Examples found in repository

examples/simple.rs (line 8)

fn main() {
    let netlist = Netlist::new("example".to_string());

    // Add the the two inputs
    let a = netlist.insert_input("a".into());
    let b = netlist.insert_input("b".into());

    // Instantiate an AND gate
    let instance = netlist
        .insert_gate(and_gate(), "inst_0".into(), &[a, b])
        .unwrap();

    // Make this AND gate an output
    instance.expose_with_name("y".into());

    // Print the netlist
    println!("{netlist}");
}

examples/dont_touch.rs (line 8)

fn main() {
    let netlist = Netlist::new("example".to_string());

    // Add the the two inputs
    let a = netlist.insert_input("a".into());
    let b = netlist.insert_input("b".into());

    // Instantiate an AND gate
    let instance = netlist
        .insert_gate(and_gate(), "inst_0".into(), &[a, b])
        .unwrap();

    // Make this AND gate an output
    instance.set_attribute("dont_touch".to_string());
    instance.expose_with_name("y".into());

    for nr in dont_touch_filter(&netlist) {
        println!("Don't touch: {nr}");
    }
}

examples/variants.rs (line 65)

fn main() {
    let netlist = Netlist::new("example".to_string());

    // Add the the two inputs
    let a = netlist.insert_input("a".into());
    let b = netlist.insert_input("b".into());

    // Instantiate an AND gate
    let instance = netlist
        .insert_gate(and_gate(), "inst_0".into(), &[a, b])
        .unwrap();

    // Make this AND gate an output
    instance.expose_with_name("y".into());

    // Print the netlist
    println!("{netlist}");
    for node in filter_nodes!(netlist, Gate::And(_, _, _)) {
        println!("Found AND gate: {node}");
    }
}

examples/lut.rs (line 110)

fn main() {
    let netlist = Netlist::new("example".to_string());

    // Add the the two inputs
    let a = netlist.insert_input("a".into());
    let b = netlist.insert_input("b".into());

    // Instantiate an NAND gate
    let instance = netlist
        .insert_gate(Lut::new(2, 7), "inst_0".into(), &[a, b])
        .unwrap();

    // Let's make it an AND gate by inverting the lookup table
    instance.get_instance_type_mut().unwrap().invert();

    // Make this LUT an output
    instance.expose_with_name("y".into());

    // Print the netlist
    println!("{netlist}");

    #[cfg(feature = "serde")]
    {
        let res = netlist.reclaim().unwrap().serialize(std::io::stdout());
        if res.is_err() {
            eprintln!("Failed to serialize netlist: {:?}", res.err());
        }
    }
}

examples/connections.rs (line 17)

fn ripple_adder() -> Netlist<Gate> {
    let netlist = Netlist::new("ripple_adder".to_string());
    let bitwidth = 4;

    // Add the the inputs
    let a_vec = netlist.insert_input_escaped_logic_bus("a".to_string(), bitwidth);
    let b_vec = netlist.insert_input_escaped_logic_bus("b".to_string(), bitwidth);
    let mut carry: DrivenNet<Gate> = netlist.insert_input("cin".into());

    for i in 0..bitwidth {
        // Instantiate a full adder for each bit
        let fa = netlist.insert_gate_disconnected(full_adder(), format_id!("fa_{i}"));

        // Connect A_i and B_i
        fa.get_input(1).connect(a_vec[i].clone());
        fa.get_input(2).connect(b_vec[i].clone());

        // Connect with the prev carry
        carry.connect(fa.get_input(0));

        // Expose the sum
        fa.expose_net(&fa.get_net(0)).unwrap();

        carry = fa.get_output(1);

        if i == bitwidth - 1 {
            // Last full adder, expose the carry out
            fa.get_net_mut(1).set_identifier("cout".into());
            fa.expose_net(&fa.get_net(1)).unwrap();
        }
    }

    netlist.reclaim().unwrap()
}

pub fn reclaim(self: Rc<Self>) -> Option<Self>

Attempts to reclaim the netlist, returning Some if successful.

Examples found in repository

examples/connections.rs (line 48)

fn ripple_adder() -> Netlist<Gate> {
    let netlist = Netlist::new("ripple_adder".to_string());
    let bitwidth = 4;

    // Add the the inputs
    let a_vec = netlist.insert_input_escaped_logic_bus("a".to_string(), bitwidth);
    let b_vec = netlist.insert_input_escaped_logic_bus("b".to_string(), bitwidth);
    let mut carry: DrivenNet<Gate> = netlist.insert_input("cin".into());

    for i in 0..bitwidth {
        // Instantiate a full adder for each bit
        let fa = netlist.insert_gate_disconnected(full_adder(), format_id!("fa_{i}"));

        // Connect A_i and B_i
        fa.get_input(1).connect(a_vec[i].clone());
        fa.get_input(2).connect(b_vec[i].clone());

        // Connect with the prev carry
        carry.connect(fa.get_input(0));

        // Expose the sum
        fa.expose_net(&fa.get_net(0)).unwrap();

        carry = fa.get_output(1);

        if i == bitwidth - 1 {
            // Last full adder, expose the carry out
            fa.get_net_mut(1).set_identifier("cout".into());
            fa.expose_net(&fa.get_net(1)).unwrap();
        }
    }

    netlist.reclaim().unwrap()
}

pub fn insert_input(self: &Rc<Self>, net: Net) -> DrivenNet<I>

Inserts an input net to the netlist

Examples found in repository

examples/simple.rs (line 11)

fn main() {
    let netlist = Netlist::new("example".to_string());

    // Add the the two inputs
    let a = netlist.insert_input("a".into());
    let b = netlist.insert_input("b".into());

    // Instantiate an AND gate
    let instance = netlist
        .insert_gate(and_gate(), "inst_0".into(), &[a, b])
        .unwrap();

    // Make this AND gate an output
    instance.expose_with_name("y".into());

    // Print the netlist
    println!("{netlist}");
}

examples/dont_touch.rs (line 11)

fn main() {
    let netlist = Netlist::new("example".to_string());

    // Add the the two inputs
    let a = netlist.insert_input("a".into());
    let b = netlist.insert_input("b".into());

    // Instantiate an AND gate
    let instance = netlist
        .insert_gate(and_gate(), "inst_0".into(), &[a, b])
        .unwrap();

    // Make this AND gate an output
    instance.set_attribute("dont_touch".to_string());
    instance.expose_with_name("y".into());

    for nr in dont_touch_filter(&netlist) {
        println!("Don't touch: {nr}");
    }
}

examples/variants.rs (line 68)

fn main() {
    let netlist = Netlist::new("example".to_string());

    // Add the the two inputs
    let a = netlist.insert_input("a".into());
    let b = netlist.insert_input("b".into());

    // Instantiate an AND gate
    let instance = netlist
        .insert_gate(and_gate(), "inst_0".into(), &[a, b])
        .unwrap();

    // Make this AND gate an output
    instance.expose_with_name("y".into());

    // Print the netlist
    println!("{netlist}");
    for node in filter_nodes!(netlist, Gate::And(_, _, _)) {
        println!("Found AND gate: {node}");
    }
}

examples/lut.rs (line 113)

fn main() {
    let netlist = Netlist::new("example".to_string());

    // Add the the two inputs
    let a = netlist.insert_input("a".into());
    let b = netlist.insert_input("b".into());

    // Instantiate an NAND gate
    let instance = netlist
        .insert_gate(Lut::new(2, 7), "inst_0".into(), &[a, b])
        .unwrap();

    // Let's make it an AND gate by inverting the lookup table
    instance.get_instance_type_mut().unwrap().invert();

    // Make this LUT an output
    instance.expose_with_name("y".into());

    // Print the netlist
    println!("{netlist}");

    #[cfg(feature = "serde")]
    {
        let res = netlist.reclaim().unwrap().serialize(std::io::stdout());
        if res.is_err() {
            eprintln!("Failed to serialize netlist: {:?}", res.err());
        }
    }
}

examples/connections.rs (line 23)

fn ripple_adder() -> Netlist<Gate> {
    let netlist = Netlist::new("ripple_adder".to_string());
    let bitwidth = 4;

    // Add the the inputs
    let a_vec = netlist.insert_input_escaped_logic_bus("a".to_string(), bitwidth);
    let b_vec = netlist.insert_input_escaped_logic_bus("b".to_string(), bitwidth);
    let mut carry: DrivenNet<Gate> = netlist.insert_input("cin".into());

    for i in 0..bitwidth {
        // Instantiate a full adder for each bit
        let fa = netlist.insert_gate_disconnected(full_adder(), format_id!("fa_{i}"));

        // Connect A_i and B_i
        fa.get_input(1).connect(a_vec[i].clone());
        fa.get_input(2).connect(b_vec[i].clone());

        // Connect with the prev carry
        carry.connect(fa.get_input(0));

        // Expose the sum
        fa.expose_net(&fa.get_net(0)).unwrap();

        carry = fa.get_output(1);

        if i == bitwidth - 1 {
            // Last full adder, expose the carry out
            fa.get_net_mut(1).set_identifier("cout".into());
            fa.expose_net(&fa.get_net(1)).unwrap();
        }
    }

    netlist.reclaim().unwrap()
}

pub fn insert_input_escaped_logic_bus( self: &Rc<Self>, net: String, bw: usize, ) -> Vec<DrivenNet<I>>

Inserts a four-state logic input port to the netlist

Examples found in repository

examples/connections.rs (line 21)

fn ripple_adder() -> Netlist<Gate> {
    let netlist = Netlist::new("ripple_adder".to_string());
    let bitwidth = 4;

    // Add the the inputs
    let a_vec = netlist.insert_input_escaped_logic_bus("a".to_string(), bitwidth);
    let b_vec = netlist.insert_input_escaped_logic_bus("b".to_string(), bitwidth);
    let mut carry: DrivenNet<Gate> = netlist.insert_input("cin".into());

    for i in 0..bitwidth {
        // Instantiate a full adder for each bit
        let fa = netlist.insert_gate_disconnected(full_adder(), format_id!("fa_{i}"));

        // Connect A_i and B_i
        fa.get_input(1).connect(a_vec[i].clone());
        fa.get_input(2).connect(b_vec[i].clone());

        // Connect with the prev carry
        carry.connect(fa.get_input(0));

        // Expose the sum
        fa.expose_net(&fa.get_net(0)).unwrap();

        carry = fa.get_output(1);

        if i == bitwidth - 1 {
            // Last full adder, expose the carry out
            fa.get_net_mut(1).set_identifier("cout".into());
            fa.expose_net(&fa.get_net(1)).unwrap();
        }
    }

    netlist.reclaim().unwrap()
}

pub fn insert_gate( self: &Rc<Self>, inst_type: I, inst_name: Identifier, operands: &[DrivenNet<I>], ) -> Result<NetRef<I>, Error>

Inserts a gate to the netlist

Examples found in repository

examples/simple.rs (line 16)

fn main() {
    let netlist = Netlist::new("example".to_string());

    // Add the the two inputs
    let a = netlist.insert_input("a".into());
    let b = netlist.insert_input("b".into());

    // Instantiate an AND gate
    let instance = netlist
        .insert_gate(and_gate(), "inst_0".into(), &[a, b])
        .unwrap();

    // Make this AND gate an output
    instance.expose_with_name("y".into());

    // Print the netlist
    println!("{netlist}");
}

examples/dont_touch.rs (line 16)

fn main() {
    let netlist = Netlist::new("example".to_string());

    // Add the the two inputs
    let a = netlist.insert_input("a".into());
    let b = netlist.insert_input("b".into());

    // Instantiate an AND gate
    let instance = netlist
        .insert_gate(and_gate(), "inst_0".into(), &[a, b])
        .unwrap();

    // Make this AND gate an output
    instance.set_attribute("dont_touch".to_string());
    instance.expose_with_name("y".into());

    for nr in dont_touch_filter(&netlist) {
        println!("Don't touch: {nr}");
    }
}

examples/variants.rs (line 73)

fn main() {
    let netlist = Netlist::new("example".to_string());

    // Add the the two inputs
    let a = netlist.insert_input("a".into());
    let b = netlist.insert_input("b".into());

    // Instantiate an AND gate
    let instance = netlist
        .insert_gate(and_gate(), "inst_0".into(), &[a, b])
        .unwrap();

    // Make this AND gate an output
    instance.expose_with_name("y".into());

    // Print the netlist
    println!("{netlist}");
    for node in filter_nodes!(netlist, Gate::And(_, _, _)) {
        println!("Found AND gate: {node}");
    }
}

examples/lut.rs (line 118)

fn main() {
    let netlist = Netlist::new("example".to_string());

    // Add the the two inputs
    let a = netlist.insert_input("a".into());
    let b = netlist.insert_input("b".into());

    // Instantiate an NAND gate
    let instance = netlist
        .insert_gate(Lut::new(2, 7), "inst_0".into(), &[a, b])
        .unwrap();

    // Let's make it an AND gate by inverting the lookup table
    instance.get_instance_type_mut().unwrap().invert();

    // Make this LUT an output
    instance.expose_with_name("y".into());

    // Print the netlist
    println!("{netlist}");

    #[cfg(feature = "serde")]
    {
        let res = netlist.reclaim().unwrap().serialize(std::io::stdout());
        if res.is_err() {
            eprintln!("Failed to serialize netlist: {:?}", res.err());
        }
    }
}

pub fn insert_gate_disconnected( self: &Rc<Self>, inst_type: I, inst_name: Identifier, ) -> NetRef<I>

Use interior mutability to add an object to the netlist. Returns a mutable reference to the created object.

Examples found in repository

examples/connections.rs (line 27)

fn ripple_adder() -> Netlist<Gate> {
    let netlist = Netlist::new("ripple_adder".to_string());
    let bitwidth = 4;

    // Add the the inputs
    let a_vec = netlist.insert_input_escaped_logic_bus("a".to_string(), bitwidth);
    let b_vec = netlist.insert_input_escaped_logic_bus("b".to_string(), bitwidth);
    let mut carry: DrivenNet<Gate> = netlist.insert_input("cin".into());

    for i in 0..bitwidth {
        // Instantiate a full adder for each bit
        let fa = netlist.insert_gate_disconnected(full_adder(), format_id!("fa_{i}"));

        // Connect A_i and B_i
        fa.get_input(1).connect(a_vec[i].clone());
        fa.get_input(2).connect(b_vec[i].clone());

        // Connect with the prev carry
        carry.connect(fa.get_input(0));

        // Expose the sum
        fa.expose_net(&fa.get_net(0)).unwrap();

        carry = fa.get_output(1);

        if i == bitwidth - 1 {
            // Last full adder, expose the carry out
            fa.get_net_mut(1).set_identifier("cout".into());
            fa.expose_net(&fa.get_net(1)).unwrap();
        }
    }

    netlist.reclaim().unwrap()
}

pub fn insert_constant( self: &Rc<Self>, value: Logic, inst_name: Identifier, ) -> Result<DrivenNet<I>, Error>

Inserts a constant Logic value to the netlist

pub fn get_driver(&self, netref: NetRef<I>, index: usize) -> Option<NetRef<I>>

Returns the driving node at input position index for netref

Panics

Panics if index is out of bounds

pub fn expose_net_with_name( &self, net: DrivenNet<I>, name: Identifier, ) -> DrivenNet<I>

Set an added object as a top-level output.

pub fn expose_net(&self, net: DrivenNet<I>) -> Result<DrivenNet<I>, Error>

Set an added object as a top-level output.

pub fn delete_net_uses(&self, netref: NetRef<I>) -> Result<Object<I>, Error>

Unlink a circuit node from the rest of the netlist. Return the object that was being stored.

pub fn replace_net_uses( &self, of: DrivenNet<I>, with: &DrivenNet<I>, ) -> Result<Object<I>, Error>

Replaces the uses of a circuit node with another circuit node. The Object stored at of is returned.

impl<I> Netlist<I>

where I: Instantiable,

pub fn get_name(&self) -> Ref<'_, String>

Returns the name of the netlist module

pub fn set_name(&self, name: String)

Sets the name of the netlist module

Panics

Panics if the module name cannot be borrowed mutably.

pub fn get_input_ports(&self) -> impl Iterator<Item = Net>

Iterates over the input ports of the netlist.

pub fn get_output_ports(&self) -> Vec<Net>

Returns a list of output nets

pub fn get_analysis<'a, A: Analysis<'a, I>>(&'a self) -> Result<A, Error>

Constructs an analysis of the netlist.

pub fn find_net(&self, net: &Net) -> Option<DrivenNet<I>>

Finds the first circuit node that drives the net. This operation is O(n). This should be unique provided the netlist is well-formed.

pub fn first(&self) -> Option<NetRef<I>>

Returns a NetRef to the first circuit node

pub fn last(&self) -> Option<NetRef<I>>

Returns a NetRef to the last circuit node

pub fn drives_an_output(&self, netref: NetRef<I>) -> bool

Returns true if an output of netref which is driving a module output.

pub fn clean_once(&self) -> Result<bool, Error>

Cleans unused nodes from the netlist, returning Ok(true) if the netlist changed.

pub fn clean(&self) -> Result<bool, Error>

Greedly removes unused nodes from the netlist, until it stops changing. Returns true if the netlist was changed.

pub fn verify(&self) -> Result<(), Error>

Verifies that a netlist is well-formed.

impl<I> Netlist<I>

where I: Instantiable,

pub fn objects(&self) -> impl Iterator<Item = NetRef<I>>

Returns an iterator over the circuit nodes in the netlist.

pub fn matches<F>(&self, filter: F) -> impl Iterator<Item = NetRef<I>>

where F: Fn(&I) -> bool,

Returns an iterator over the circuit nodes that match the instance type.

pub fn inputs(&self) -> impl Iterator<Item = DrivenNet<I>>

Returns an iterator to principal inputs in the netlist as references.

pub fn outputs(&self) -> Vec<(DrivenNet<I>, Net)>

Returns an iterator to circuit nodes that drive an output in the netlist.

pub fn connections(&self) -> impl Iterator<Item = Connection<I>>

Returns an iterator over the wire connections in the netlist.

pub fn dfs(&self, from: NetRef<I>) -> impl Iterator<Item = NetRef<I>>

Returns a depth-first search iterator over the nodes in the netlist.

Trait Implementations

impl<I> Debug for Netlist<I>

where I: Instantiable + Debug,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<I> Display for Netlist<I>

where I: Instantiable,

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<'a, I> IntoIterator for &'a Netlist<I>

where I: Instantiable,

type Item = Net

The type of the elements being iterated over.

type IntoIter = NetIterator<'a, I>

Which kind of iterator are we turning this into?

fn into_iter(self) -> Self::IntoIter

Creates an iterator from a value.