Enum Op

Source

pub enum Op {
Show 118 variants    Lui {
        rd: usize,
        u_imm: i32,
    },
    Auipc {
        rd: usize,
        u_imm: i32,
    },
    Jal {
        rd: usize,
        j_imm: i32,
    },
    Jalr {
        rd: usize,
        rs1: usize,
        i_imm: i32,
    },
    Beq {
        rs1: usize,
        rs2: usize,
        b_imm: i32,
    },
    Bne {
        rs1: usize,
        rs2: usize,
        b_imm: i32,
    },
    Blt {
        rs1: usize,
        rs2: usize,
        b_imm: i32,
    },
    Bge {
        rs1: usize,
        rs2: usize,
        b_imm: i32,
    },
    Bltu {
        rs1: usize,
        rs2: usize,
        b_imm: i32,
    },
    Bgeu {
        rs1: usize,
        rs2: usize,
        b_imm: i32,
    },
    Lb {
        rd: usize,
        rs1: usize,
        i_imm: i32,
    },
    Lh {
        rd: usize,
        rs1: usize,
        i_imm: i32,
    },
    Lw {
        rd: usize,
        rs1: usize,
        i_imm: i32,
    },
    Lbu {
        rd: usize,
        rs1: usize,
        i_imm: i32,
    },
    Lhu {
        rd: usize,
        rs1: usize,
        i_imm: i32,
    },
    Sb {
        rs1: usize,
        rs2: usize,
        s_imm: i32,
    },
    Sh {
        rs1: usize,
        rs2: usize,
        s_imm: i32,
    },
    Sw {
        rs1: usize,
        rs2: usize,
        s_imm: i32,
    },
    Addi {
        rd: usize,
        rs1: usize,
        i_imm: i32,
    },
    Slti {
        rd: usize,
        rs1: usize,
        i_imm: i32,
    },
    Sltiu {
        rd: usize,
        rs1: usize,
        i_imm: i32,
    },
    Xori {
        rd: usize,
        rs1: usize,
        i_imm: i32,
    },
    Ori {
        rd: usize,
        rs1: usize,
        i_imm: i32,
    },
    Andi {
        rd: usize,
        rs1: usize,
        i_imm: i32,
    },
    Slli {
        rd: usize,
        rs1: usize,
        shamt: u32,
    },
    Srli {
        rd: usize,
        rs1: usize,
        shamt: u32,
    },
    Srai {
        rd: usize,
        rs1: usize,
        shamt: u32,
    },
    Add {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Sll {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Slt {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Sltu {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Xor {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Srl {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Or {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    And {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Sub {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Sra {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Fence {
        pred: u32,
        succ: u32,
    },
    FenceI,
    Ecall,
    Ebreak,
    Csrrw {
        rd: usize,
        rs1: usize,
        csr: u32,
    },
    Csrrs {
        rd: usize,
        rs1: usize,
        csr: u32,
    },
    Csrrc {
        rd: usize,
        rs1: usize,
        csr: u32,
    },
    Csrrwi {
        rd: usize,
        zimm: u32,
        csr: u32,
    },
    Csrrsi {
        rd: usize,
        zimm: u32,
        csr: u32,
    },
    Csrrci {
        rd: usize,
        zimm: u32,
        csr: u32,
    },
    Mul {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Mulh {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Mulhsu {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Mulhu {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Div {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Divu {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Rem {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    Remu {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    LrW {
        rd: usize,
        rs1: usize,
        aq: bool,
        rl: bool,
    },
    ScW {
        rd: usize,
        rs1: usize,
        rs2: usize,
        aq: bool,
        rl: bool,
    },
    AmoswapW {
        rd: usize,
        rs1: usize,
        rs2: usize,
        aq: bool,
        rl: bool,
    },
    AmoaddW {
        rd: usize,
        rs1: usize,
        rs2: usize,
        aq: bool,
        rl: bool,
    },
    AmoxorW {
        rd: usize,
        rs1: usize,
        rs2: usize,
        aq: bool,
        rl: bool,
    },
    AmoandW {
        rd: usize,
        rs1: usize,
        rs2: usize,
        aq: bool,
        rl: bool,
    },
    AmoorW {
        rd: usize,
        rs1: usize,
        rs2: usize,
        aq: bool,
        rl: bool,
    },
    AmominW {
        rd: usize,
        rs1: usize,
        rs2: usize,
        aq: bool,
        rl: bool,
    },
    AmomaxW {
        rd: usize,
        rs1: usize,
        rs2: usize,
        aq: bool,
        rl: bool,
    },
    AmominuW {
        rd: usize,
        rs1: usize,
        rs2: usize,
        aq: bool,
        rl: bool,
    },
    AmomaxuW {
        rd: usize,
        rs1: usize,
        rs2: usize,
        aq: bool,
        rl: bool,
    },
    Flw {
        rd: usize,
        rs1: usize,
        i_imm: i32,
    },
    Fsw {
        rs1: usize,
        rs2: usize,
        s_imm: i32,
    },
    FmaddS {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rs3: usize,
        rm: u32,
    },
    FmsubS {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rs3: usize,
        rm: u32,
    },
    FnmsubS {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rs3: usize,
        rm: u32,
    },
    FnmaddS {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rs3: usize,
        rm: u32,
    },
    FaddS {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rm: u32,
    },
    FsubS {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rm: u32,
    },
    FmulS {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rm: u32,
    },
    FdivS {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rm: u32,
    },
    FsqrtS {
        rd: usize,
        rs1: usize,
        rm: u32,
    },
    FsgnjS {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FsgnjnS {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FsgnjxS {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FminS {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FmaxS {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FcvtWS {
        rd: usize,
        rs1: usize,
        rm: u32,
    },
    FcvtWuS {
        rd: usize,
        rs1: usize,
        rm: u32,
    },
    FmvXW {
        rd: usize,
        rs1: usize,
    },
    FeqS {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FltS {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FleS {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FclassS {
        rd: usize,
        rs1: usize,
    },
    FcvtSW {
        rd: usize,
        rs1: usize,
        rm: u32,
    },
    FcvtSWu {
        rd: usize,
        rs1: usize,
        rm: u32,
    },
    FmvWX {
        rd: usize,
        rs1: usize,
    },
    Fld {
        rd: usize,
        rs1: usize,
        i_imm: i32,
    },
    Fsd {
        rs1: usize,
        rs2: usize,
        s_imm: i32,
    },
    FmaddD {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rs3: usize,
        rm: u32,
    },
    FmsubD {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rs3: usize,
        rm: u32,
    },
    FnmsubD {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rs3: usize,
        rm: u32,
    },
    FnmaddD {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rs3: usize,
        rm: u32,
    },
    FaddD {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rm: u32,
    },
    FsubD {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rm: u32,
    },
    FmulD {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rm: u32,
    },
    FdivD {
        rd: usize,
        rs1: usize,
        rs2: usize,
        rm: u32,
    },
    FsqrtD {
        rd: usize,
        rs1: usize,
        rm: u32,
    },
    FsgnjD {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FsgnjnD {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FsgnjxD {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FminD {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FmaxD {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FcvtWD {
        rd: usize,
        rs1: usize,
        rm: u32,
    },
    FcvtWuD {
        rd: usize,
        rs1: usize,
        rm: u32,
    },
    FeqD {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FltD {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FleD {
        rd: usize,
        rs1: usize,
        rs2: usize,
    },
    FclassD {
        rd: usize,
        rs1: usize,
    },
    FcvtDW {
        rd: usize,
        rs1: usize,
        rm: u32,
    },
    FcvtDWu {
        rd: usize,
        rs1: usize,
        rm: u32,
    },
    FcvtSD {
        rd: usize,
        rs1: usize,
        rm: u32,
    },
    FcvtDS {
        rd: usize,
        rs1: usize,
        rm: u32,
    },
}