Enum Inst 

#[non_exhaustive]
pub enum Inst {
    Lui {
        uimm: Imm,
        dest: Reg,
    },
    Auipc {
        uimm: Imm,
        dest: Reg,
    },
    Jal {
        offset: Imm,
        dest: Reg,
    },
    Jalr {
        offset: Imm,
        base: Reg,
        dest: Reg,
    },
    Beq {
        offset: Imm,
        src1: Reg,
        src2: Reg,
    },
    Bne {
        offset: Imm,
        src1: Reg,
        src2: Reg,
    },
    Blt {
        offset: Imm,
        src1: Reg,
        src2: Reg,
    },
    Bge {
        offset: Imm,
        src1: Reg,
        src2: Reg,
    },
    Bltu {
        offset: Imm,
        src1: Reg,
        src2: Reg,
    },
    Bgeu {
        offset: Imm,
        src1: Reg,
        src2: Reg,
    },
    Lb {
        offset: Imm,
        dest: Reg,
        base: Reg,
    },
    Lbu {
        offset: Imm,
        dest: Reg,
        base: Reg,
    },
    Lh {
        offset: Imm,
        dest: Reg,
        base: Reg,
    },
    Lhu {
        offset: Imm,
        dest: Reg,
        base: Reg,
    },
    Lw {
        offset: Imm,
        dest: Reg,
        base: Reg,
    },
    Lwu {
        offset: Imm,
        dest: Reg,
        base: Reg,
    },
    Ld {
        offset: Imm,
        dest: Reg,
        base: Reg,
    },
    Sb {
        offset: Imm,
        src: Reg,
        base: Reg,
    },
    Sh {
        offset: Imm,
        src: Reg,
        base: Reg,
    },
    Sw {
        offset: Imm,
        src: Reg,
        base: Reg,
    },
    Sd {
        offset: Imm,
        src: Reg,
        base: Reg,
    },
    Addi {
        imm: Imm,
        dest: Reg,
        src1: Reg,
    },
    AddiW {
        imm: Imm,
        dest: Reg,
        src1: Reg,
    },
    Slti {
        imm: Imm,
        dest: Reg,
        src1: Reg,
    },
    Sltiu {
        imm: Imm,
        dest: Reg,
        src1: Reg,
    },
    Xori {
        imm: Imm,
        dest: Reg,
        src1: Reg,
    },
    Ori {
        imm: Imm,
        dest: Reg,
        src1: Reg,
    },
    Andi {
        imm: Imm,
        dest: Reg,
        src1: Reg,
    },
    Slli {
        imm: Imm,
        dest: Reg,
        src1: Reg,
    },
    SlliW {
        imm: Imm,
        dest: Reg,
        src1: Reg,
    },
    Srli {
        imm: Imm,
        dest: Reg,
        src1: Reg,
    },
    SrliW {
        imm: Imm,
        dest: Reg,
        src1: Reg,
    },
    Srai {
        imm: Imm,
        dest: Reg,
        src1: Reg,
    },
    SraiW {
        imm: Imm,
        dest: Reg,
        src1: Reg,
    },
    Add {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    AddW {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Sub {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    SubW {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Sll {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    SllW {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Slt {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Sltu {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Xor {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Srl {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    SrlW {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Sra {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    SraW {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Or {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    And {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Fence {
        fence: Fence,
    },
    Ecall,
    Ebreak,
    Mul {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    MulW {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Mulh {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Mulhsu {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Mulhu {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Div {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    DivW {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Divu {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    DivuW {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Rem {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    RemW {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    Remu {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    RemuW {
        dest: Reg,
        src1: Reg,
        src2: Reg,
    },
    LrW {
        order: AmoOrdering,
        dest: Reg,
        addr: Reg,
    },
    ScW {
        order: AmoOrdering,
        dest: Reg,
        addr: Reg,
        src: Reg,
    },
    AmoW {
        order: AmoOrdering,
        op: AmoOp,
        dest: Reg,
        addr: Reg,
        src: Reg,
    },
}

A RISC-V instruction.

Every variant is a different instruction, with immediates as u32. For instructions that sign-extend immediates, the immediates will have been sign-extended already, so the value can be used as-is. For instructions that have immediates in the upper bits (lui, auipc), the shift will have been done already, so the value can also be used as-is.

Variants (Non-exhaustive)

Non-exhaustive enums could have additional variants added in future. Therefore, when matching against variants of non-exhaustive enums, an extra wildcard arm must be added to account for any future variants.

Lui

Load Upper Immediate

Fields

uimm: Imm

dest: Reg

Auipc

Add Upper Immediate to PC

Fields

uimm: Imm

dest: Reg

Jal

Jump And Link

Fields

offset: Imm

dest: Reg

Jalr

Jump And Link Register (indirect)

Fields

offset: Imm

base: Reg

dest: Reg

Beq

Branch Equal

Fields

offset: Imm

src1: Reg

src2: Reg

Bne

Branch Not Equal

Fields

offset: Imm

src1: Reg

src2: Reg

Blt

Branch Less Than (signed)

Fields

offset: Imm

src1: Reg

src2: Reg

Bge

Branch Greater or Equal (signed)

Fields

offset: Imm

src1: Reg

src2: Reg

Bltu

Branch Less Than Unsigned

Fields

offset: Imm

src1: Reg

src2: Reg

Bgeu

Branch Greater or Equal Unsigned

Fields

offset: Imm

src1: Reg

src2: Reg

Lb

Load Byte (sign-ext)

Fields

offset: Imm

dest: Reg

base: Reg

Lbu

Load Unsigned Byte (zero-ext)

Fields

offset: Imm

dest: Reg

base: Reg

Lh

Load Half (sign-ext)

Fields

offset: Imm

dest: Reg

base: Reg

Lhu

Load Unsigned Half (zero-ext)

Fields

offset: Imm

dest: Reg

base: Reg

Lw

Load Word (on RV64: sign-ext)

Fields

offset: Imm

dest: Reg

base: Reg

Lwu

Load Word (zero-ext) (RV64 only)

Fields

offset: Imm

dest: Reg

base: Reg

Ld

Load Doubleword (RV64 only)

Fields

offset: Imm

dest: Reg

base: Reg

Sb

Store Byte

Fields

offset: Imm

src: Reg

base: Reg

Sh

Store Half

Fields

offset: Imm

src: Reg

base: Reg

Sw

Store Word

Fields

offset: Imm

src: Reg

base: Reg

Sd

Store Doubleword (RV64 only)

Fields

offset: Imm

src: Reg

base: Reg

Addi

Add Immediate

Fields

imm: Imm

dest: Reg

src1: Reg

AddiW

Add Immediate 32-bit (RV64 only)

Fields

imm: Imm

dest: Reg

src1: Reg

Slti

Set Less Than Immediate (signed)

Fields

imm: Imm

dest: Reg

src1: Reg

Sltiu

Set Less Than Immediate Unsigned

Fields

imm: Imm

dest: Reg

src1: Reg

Xori

XOR Immediate

Fields

imm: Imm

dest: Reg

src1: Reg

Ori

OR Immediate

Fields

imm: Imm

dest: Reg

src1: Reg

Andi

AND Immediate

Fields

imm: Imm

dest: Reg

src1: Reg

Slli

Shift Left Logical Immediate

Fields

imm: Imm

dest: Reg

src1: Reg

SlliW

Shift Left Logical Immediate 32-bit (RV64 only)

Fields

imm: Imm

dest: Reg

src1: Reg

Srli

Shift Right Logical Immediate (unsigned)

Fields

imm: Imm

dest: Reg

src1: Reg

SrliW

Shift Right Logical Immediate (unsigned) 32-bit (RV64 only)

Fields

imm: Imm

dest: Reg

src1: Reg

Srai

Shift Right Arithmetic Immediate (signed)

Fields

imm: Imm

dest: Reg

src1: Reg

SraiW

Shift Right Arithmetic Immediate (signed) 32-bit (RV64 only)

Fields

imm: Imm

dest: Reg

src1: Reg

Add

Add

Fields

dest: Reg

src1: Reg

src2: Reg

AddW

Add 32-bit (RV64 only)

Fields

dest: Reg

src1: Reg

src2: Reg

Sub

Subtract

Fields

dest: Reg

src1: Reg

src2: Reg

SubW

Subtract 32-bit (RV64 only)

Fields

dest: Reg

src1: Reg

src2: Reg

Sll

Shift Left Logical

Fields

dest: Reg

src1: Reg

src2: Reg

SllW

Shift Left Logical 32-bit (RV64 only)

Fields

dest: Reg

src1: Reg

src2: Reg

Slt

Set Less Than (signed)

Fields

dest: Reg

src1: Reg

src2: Reg

Sltu

Set Less Than Unsigned

Fields

dest: Reg

src1: Reg

src2: Reg

Xor

XOR

Fields

dest: Reg

src1: Reg

src2: Reg

Srl

Shift Right Logical (unsigned)

Fields

dest: Reg

src1: Reg

src2: Reg

SrlW

Shift Right Logical (unsigned) 32-bit (RV64 only)

Fields

dest: Reg

src1: Reg

src2: Reg

Sra

Shift Right Arithmetic (unsigned)

Fields

dest: Reg

src1: Reg

src2: Reg

SraW

Shift Right Arithmetic (unsigned) 32-bit (RV64 only)

Fields

dest: Reg

src1: Reg

src2: Reg

Or

OR

Fields

dest: Reg

src1: Reg

src2: Reg

And

AND

Fields

dest: Reg

src1: Reg

src2: Reg

Fence

Memory Fence

Fields

fence: Fence

Ecall

ECALL, call into environment

Ebreak

EBREAK, break into debugger

Mul

Multiply

Fields

dest: Reg

src1: Reg

src2: Reg

MulW

Multiply 32-bit (RV64 only)

Fields

dest: Reg

src1: Reg

src2: Reg

Mulh

Mul Upper Half Signed-Signed

Fields

dest: Reg

src1: Reg

src2: Reg

Mulhsu

Mul Upper Half Signed-Unsigned

Fields

dest: Reg

src1: Reg

src2: Reg

Mulhu

Mul Upper Half Unsigned-Unsigned

Fields

dest: Reg

src1: Reg

src2: Reg

Div

Divide (signed)

Fields

dest: Reg

src1: Reg

src2: Reg

DivW

Divide (signed) 32-bit (RV64 only)

Fields

dest: Reg

src1: Reg

src2: Reg

Divu

Divide Unsigned

Fields

dest: Reg

src1: Reg

src2: Reg

DivuW

Divide Unsigned 32-bit (RV64 only)

Fields

dest: Reg

src1: Reg

src2: Reg

Rem

Remainder (signed)

Fields

dest: Reg

src1: Reg

src2: Reg

RemW

Remainder (signed) 32-bit (RV64 only)

Fields

dest: Reg

src1: Reg

src2: Reg

Remu

Remainder Unsigned

Fields

dest: Reg

src1: Reg

src2: Reg

RemuW

Remainder Unsigned 32-bit (RV64 only)

Fields

dest: Reg

src1: Reg

src2: Reg

LrW

Load-Reserved Word

Fields

order: AmoOrdering

dest: Reg

addr: Reg

ScW

Store-Conditional Word

Fields

order: AmoOrdering

dest: Reg

addr: Reg

src: Reg

AmoW

Atomic Memory Operation

Fields

order: AmoOrdering

op: AmoOp

dest: Reg

addr: Reg

src: Reg

Implementations

impl Inst

pub fn first_byte_is_compressed(byte: u8) -> bool

Whether the first byte of an instruction indicates a compressed or uncompressed instruction.

Examples

// addi sp, sp, -0x20 (compressed)
let x = 0x1101_u32;
assert!(rvdc::Inst::first_byte_is_compressed(x.to_le_bytes()[0]));
let x = 0x1101_u16;
assert!(rvdc::Inst::first_byte_is_compressed(x.to_le_bytes()[0]));

// auipc t1, 0xa
let x = 0x0000a317_u32;
assert!(!rvdc::Inst::first_byte_is_compressed(x.to_le_bytes()[0]));

pub fn decode( code: u32, xlen: Xlen, ) -> Result<(Inst, IsCompressed), DecodeError>

Decode an instruction from four bytes.

The instruction may be compressed, in which case only two bytes are consumed. Even in these cases, the full next four bytes must be passed.

If the caller wants to avoid reading more bytes than necessary, Self::first_byte_is_compressed can be used to check, read the required bytes, and then call Self::decode_compressed or Self::decode_normal directly.

pub fn decode_compressed(code: u16, xlen: Xlen) -> Result<Inst, DecodeError>

Decode a known compressed instruction from its two bytes.

Example

// Compressed addi sp, sp, -0x20
let x = 0x1101_u16;
let expected = rvdc::Inst::Addi { imm: rvdc::Imm::new_i32(-0x20), dest: rvdc::Reg::SP, src1: rvdc::Reg::SP };

let inst = rvdc::Inst::decode_compressed(x, rvdc::Xlen::Rv32).unwrap();
assert_eq!(inst, expected);

pub fn decode_normal(code: u32, xlen: Xlen) -> Result<Inst, DecodeError>

Decode a normal (not compressed) instruction.

pub fn encode_normal(&self, xlen: Xlen) -> u32

Encode a normal (not compressed) instruction

Trait Implementations

impl Clone for Inst

fn clone(&self) -> Inst

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Inst

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Display for Inst

Prints the instruction in disassembled form.

Note that the precise output here is not considered stable.

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Hash for Inst

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for Inst

fn eq(&self, other: &Inst) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Copy for Inst

impl Eq for Inst

impl StructuralPartialEq for Inst