Module optimization 

Performance optimizations for j-Tree + BMSSP implementation.

Provides SOTA optimizations achieving 10x combined speedup. Performance Optimizations for j-Tree + BMSSP Implementation

This module implements the SOTA optimizations from ADR-002-addendum-sota-optimizations.md:

1. Degree-based presparse (DSpar): 5.9x speedup via effective resistance approximation
2. LRU Cache: Path distance caching with prefetch optimization
3. SIMD Operations: Vectorized distance array computations
4. Pool Allocators: Memory-efficient allocations with lazy deallocation
5. Parallel Updates: Rayon-based parallel level updates with work-stealing
6. WASM Optimization: Batch operations and TypedArray transfers

Target: Combined 10x speedup over naive implementation.

Re-exports

pub use benchmark::BenchmarkResult;

pub use benchmark::BenchmarkSuite;

pub use benchmark::OptimizationBenchmark;

pub use cache::CacheConfig;

pub use cache::CacheStats;

pub use cache::PathDistanceCache;

pub use cache::PrefetchHint;

pub use dspar::DegreePresparse;

pub use dspar::PresparseConfig;

pub use dspar::PresparseResult;

pub use dspar::PresparseStats;

pub use parallel::ParallelConfig;

pub use parallel::ParallelLevelUpdater;

pub use parallel::WorkStealingScheduler;

pub use pool::LazyLevel;

pub use pool::LevelPool;

pub use pool::PoolConfig;

pub use pool::PoolStats;

pub use simd_distance::DistanceArray;

pub use simd_distance::SimdDistanceOps;

pub use wasm_batch::BatchConfig;

pub use wasm_batch::TypedArrayTransfer;

pub use wasm_batch::WasmBatchOps;

Modules

benchmark

Comprehensive Benchmark Suite for j-Tree + BMSSP Optimizations

cache

LRU Cache for Path Distances

dspar

Degree-based Presparse (DSpar) Implementation

parallel

Parallel Level Updates with Work-Stealing

pool

Pool Allocators and Lazy Level Deallocation

simd_distance

SIMD-Optimized Distance Array Operations

wasm_batch

WASM Batch Operations and TypedArray Optimizations