pub struct AmdGpu {
pub pci_slot: String,
pub pci_device_id: String,
pub marketing_name: Option<String>,
pub gfx_arch: Option<String>,
pub vram_bytes: Option<u64>,
pub is_integrated: bool,
pub rocm_index: Option<u32>,
}Expand description
AMD discrete GPU discovered via sysfs.
All fields optional except pci_slot and is_integrated. Detectors
populate from /sys/class/drm/card*/device and PCI tables.
Fields§
§pci_slot: StringPCI slot in BB:DD.F form (canonicalized, no 0000: prefix).
pci_device_id: StringPCI device ID (hex string, e.g. "0x744c" for Navi 31).
marketing_name: Option<String>Marketing name from lspci/rocminfo if available.
gfx_arch: Option<String>gfx architecture (e.g. "gfx1100" for Navi 31).
vram_bytes: Option<u64>Total VRAM in bytes from mem_info_vram_total.
is_integrated: booltrue if classified as integrated by device_is_integrated.
rocm_index: Option<u32>Real ROCm (HSA) agent index from rocminfo, when available.
This is the authoritative device index for ROCR_VISIBLE_DEVICES /
HIP_VISIBLE_DEVICES: those vars filter by the original enumeration
order (CPU + iGPU + dGPU agents as rocminfo prints them), NOT a
re-numbered post-filter sequence. On an APU+dGPU host where the iGPU is
ROCr agent 2 and the dGPU is agent 3, the visibility mask must be 3,
not the compacted 0 produced by enumerating the filtered dGPU list.
None when rocminfo is unavailable; callers fall back to compacted
indices (the historical sysfs-only behavior) in that case.
Trait Implementations§
Auto Trait Implementations§
impl Freeze for AmdGpu
impl RefUnwindSafe for AmdGpu
impl Send for AmdGpu
impl Sync for AmdGpu
impl Unpin for AmdGpu
impl UnsafeUnpin for AmdGpu
impl UnwindSafe for AmdGpu
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