Module fifo 

TlmFifo<T>: the UVM uvm_tlm_fifo — a component that encapsulates a queue (pyuvm’s Queue/Mailbox) so two components connect to the same FIFO and neither learns the other exists (D17/D23/D24; pyuvm uvm_tlm_fifo, default depth 1).

This encapsulation is the FIFO’s point, not a nice-to-have: it is what makes the connection late-bound. Hierarchy visibility is a consequence; decoupling is the reason. Do not treat the FIFO as optional plumbing.

Ports and exports

A component that needs a FIFO it does not own declares a port (crate::port::PutPort, crate::port::GetPort, crate::port::PeekPort). The component that owns the FIFO hands out exports and connects them:

self.fifo.put_export().connect(&self.producer, Producer::PUT_PORT);
self.fifo.get_export().connect(&self.consumer, Consumer::GET_PORT);

The export always initiates, as in the UVM. See crate::port for why the first argument works for an erased child and for self alike.

Structs

GetExport

The FIFO’s get side.

PeekExport

The FIFO’s peek side.

PutExport

The FIFO’s put side, handed to a component that needs to put.

TapExport

One of a FIFO’s analysis taps (D23): connect a subscriber to watch the traffic without joining the data path.

TlmFifo

A bounded (or unbounded) FIFO that is also a component in the hierarchy.