Struct rustduino::atmega328p::com::i2c::Twi

#[repr(C, packed)]
pub struct Twi { /* fields omitted */ }

Contains registers fow TWI.

• TWBR: TWI Bit Rate Register. TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the master modes. See [Section 21.5.2 “Bit Rate Generator Unit”]

• TWSR: TWI Status Register. The first 5 bits of TWSR reflect the status of the TWI logic and te 2-wire Serial bus. The last 2 bits decide the bit rate prescaler.

• TWAR: TWI (Slave) Address Register. The TWAR should be loaded with the 7-bit slave address (in the seven most significant bits of TWAR) to which the TWI will respond when programmed as a slave transmitter or receiver, and not needed in the master modes.

• TWDR: TWI Data Register. n transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the data register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined.

• TWSR: TWI Status Register. The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a master access by applying a START condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible

• TWAMR: TWI Address Mask. The TWAMR can be loaded with a 7-bit slave address mask. Each of the bits in TWAMR can mask (disable) the corresponding address bits in the TWI address register (TWAR). If the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in TWAR.

Implementations

impl Twi

pub fn new() -> &'static mut Self

Returns a pointer to TWBR.

Returns

• a reference to Twi struct object - Which would be used to control the implementation.

pub fn wait_to_complete(&mut self, operation: u8) -> bool

Waits for the process to be complete. Times out if TWINT is not set in 100 seconds.

Returns

• a boolean - Which is true if the TWI is ready, false otherwise.

pub fn init(&mut self)

Iniates the TWI bus.

pub fn start(&mut self) -> bool

Sends a Start Signal

Returns

• a boolean - Which is true if process is successful, false otherwise.

pub fn rep_start(&mut self) -> bool

Sends a Repeat Start Signal

Returns

• a boolean - Which is true if process is successful, false otherwise.

pub fn stop(&mut self)

Stops the TWI bus.

pub fn set_address(&mut self, addr: u8) -> bool

Sets address of Slave. Used in Master Slave Mode.

Arguments

• addr - It is passed into the function and is a seven bit integer used for location of implementation.

Returns

• a boolean - Which is true if the checking process is sucessful otherwise false.

pub fn address_read(&mut self, address: u8) -> bool

Checks if slave is acknowledged.

Arguments

• address - It is passed into the function and is a seven bit integer used for location of implementation.

Returns

• a boolean - Which is true if the checking process is sucessful otherwise false.

pub fn write(&mut self, data: u8) -> bool

Writes one byte of data to the Slave. Need to set address first.

Arguments

• data - a u8, the integer which is to be written.

Returns

• a boolean - Whcih is true if process is successful otherwise false.

pub fn write_burst(&mut self, data: &FixedSliceVec<'_, u8>) -> usize

Writes consecutive bytes of data to the Slave. Need to set address first.

Arguments

• data - a sliced vector consisting of u8, which is filled with the data read.

Returns

• a usize integer - Which gives the critical length of the data bus above which no data could be written.

pub fn read_ack(&mut self, data: &mut FixedSliceVec<'_, u8>) -> bool

Appends the value in TWCR to the given vector.

Arguments

• data - a sliced vector consisting of u8, which will be filled with the data read.

Returns

• a boolean - Which is true if process is completed otherwise false.

pub fn read_ack_burst(
    &mut self,
    data: &mut FixedSliceVec<'_, u8>,
    length: usize
) -> usize

Appends the value in TWCR to the given vector. Need to set address first.

Arguments

• data - a sliced vector consisting of u8, which is filled with the data read.
• length - a usize integer, which is the theoretically set value of length of the sliced vector data.

Returns

• a usize integer - Which gives the critical length of the data bus above which no data exists.

pub fn read_nack(&mut self, data: &mut FixedSliceVec<'_, u8>) -> bool

Reads the nack value data in TWCR to the given vector.

Arguments

• data - a sliced vector consisting of u8, which will be filled with the data read.

Returns

• a boolean - Which is true if process is completed otherwise false.

pub fn read_nack_burst(
    &mut self,
    data: &mut FixedSliceVec<'_, u8>,
    length: usize
) -> usize

Reads the nack value data in TWCR to the given vector.

Arguments

• data - a sliced vector consisting of u8, which is filled with the data read.
• length - a usize integer, which is the theoretically set value of length of the sliced vector data.

Returns

• a usize integer - Which gives the critical length of the data bus above which no data exists.

pub fn write_to_slave(
    &mut self,
    address: u8,
    data: &FixedSliceVec<'_, u8>
) -> bool

Writes consecutive Data bytes to slave

Returns

• a boolean - Which is true if process is completed and aborts if any of the steps, i.e start, setting address or writing fails.

pub fn read_from_slave(
    &mut self,
    address: u8,
    length: usize,
    data: &mut FixedSliceVec<'_, u8>
) -> bool

Reads consecutive Data bytes from slave Requires number of bytes ro be read

Arguments

• address - a u8, consisting the target address of the read implementation.
• length - a usize integer, showing the number of bytes to read.
• data - a sliced vector consisting of u8, where the data will be stored after reading.

Returns

• a boolean - Which is true if process is completed otherwise false and aborts the process if any of the steps, i.e start, reading address, reading ACK or reading NACK fails.