Struct rust_hdl::widgets::fifo::cross_fifo::CrossNarrowFIFO

pub struct CrossNarrowFIFO<const DW: usize, const WN: usize, const WNP1: usize, const DN: usize, const NN: usize, const NNP1: usize> {
    pub data_in: Signal<In, Bits<DW>>,
    pub write: Signal<In, Bit>,
    pub full: Signal<Out, Bit>,
    pub write_clock: Signal<In, Clock>,
    pub data_out: Signal<Out, Bits<DN>>,
    pub read: Signal<In, Bit>,
    pub empty: Signal<Out, Bit>,
    pub read_clock: Signal<In, Clock>,
    pub in_fifo: AsynchronousFIFO<Bits<DW>, WN, WNP1, 1>,
    pub out_fifo: SynchronousFIFO<Bits<DN>, NN, NNP1, 1>,
    pub reducer: FIFOReducerN<DW, DN>,
}

Fields

data_in: Signal<In, Bits<DW>>

write: Signal<In, Bit>

full: Signal<Out, Bit>

write_clock: Signal<In, Clock>

data_out: Signal<Out, Bits<DN>>

read: Signal<In, Bit>

empty: Signal<Out, Bit>

read_clock: Signal<In, Clock>

in_fifo: AsynchronousFIFO<Bits<DW>, WN, WNP1, 1>

out_fifo: SynchronousFIFO<Bits<DN>, NN, NNP1, 1>

reducer: FIFOReducerN<DW, DN>

Implementations

impl<const DW: usize, const WN: usize, const WNP1: usize, const DN: usize, const NN: usize, const NNP1: usize> CrossNarrowFIFO<DW, WN, WNP1, DN, NN, NNP1>

pub fn new(order: WordOrder) -> Self

Trait Implementations

impl<const DW: usize, const WN: usize, const WNP1: usize, const DN: usize, const NN: usize, const NNP1: usize> Block for CrossNarrowFIFO<DW, WN, WNP1, DN, NN, NNP1>

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl<const DW: usize, const WN: usize, const WNP1: usize, const DN: usize, const NN: usize, const NNP1: usize> Default for CrossNarrowFIFO<DW, WN, WNP1, DN, NN, NNP1>

fn default() -> Self

Returns the “default value” for a type.

impl<const DW: usize, const WN: usize, const WNP1: usize, const DN: usize, const NN: usize, const NNP1: usize> Logic for CrossNarrowFIFO<DW, WN, WNP1, DN, NN, NNP1>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog