Struct rust_hdl::bsp::ok_xem6010::ddr_fifo::DDRFIFO

pub struct DDRFIFO {

    pub o_clock: Signal<Out, Clock>,
    pub raw_sys_clock: Signal<In, Clock>,
    pub reset: Signal<In, Bit>,
    pub read: Signal<In, Bit>,
    pub data_out: Signal<Out, Bits<32>>,
    pub empty: Signal<Out, Bit>,
    pub almost_empty: Signal<Out, Bit>,
    pub read_clock: Signal<In, Clock>,
    pub write: Signal<In, Bit>,
    pub data_in: Signal<In, Bits<32>>,
    pub almost_full: Signal<Out, Bit>,
    pub full: Signal<Out, Bit>,
    pub write_clock: Signal<In, Clock>,
    pub mcb: MCBInterface1GDDR2,
    pub status: Signal<Out, Bits<8>>,
    /* private fields */
}

Fields

o_clock: Signal<Out, Clock>

raw_sys_clock: Signal<In, Clock>

reset: Signal<In, Bit>

read: Signal<In, Bit>

data_out: Signal<Out, Bits<32>>

empty: Signal<Out, Bit>

almost_empty: Signal<Out, Bit>

read_clock: Signal<In, Clock>

write: Signal<In, Bit>

data_in: Signal<In, Bits<32>>

almost_full: Signal<Out, Bit>

full: Signal<Out, Bit>

write_clock: Signal<In, Clock>

mcb: MCBInterface1GDDR2

status: Signal<Out, Bits<8>>

Trait Implementations

impl Block for DDRFIFO

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl Default for DDRFIFO

fn default() -> DDRFIFO

Returns the “default value” for a type.

impl Logic for DDRFIFO

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog