rust-hdl-0.46.0
- rust-hdl 0.46.0
- Docs.rs crate page
- MIT
- Links
- Homepage
- Repository
- crates.io
- Source
- Owners
- samitbasu
- Dependencies
- anyhow ^1 normal
  
  array-init ^2.0.0 normal
  
  crossbeam ^0.8.1 normal
  
  embed-doc-image ^0.1.4 normal
  
  evalexpr ^6.3.0 normal
  
  num-bigint ^0.4.0 normal
  
  num-traits ^0.2.14 normal
  
  petgraph ^0.6.0 normal
  
  rand ^0.8 normal
  
  regex ^1.5.4 normal
  
  rust-hdl-core ^0.46.0 normal
  
  rust-hdl-fpga-support ^0.46.0 normal optional
  
  rust-hdl-hls ^0.46.0 normal
  
  rust-hdl-macros ^0.46.0 normal
  
  rust-hdl-sim ^0.46.0 normal
  
  rust-hdl-widgets ^0.46.0 normal
  
  seq-macro ^0.3.1 normal
  
  substring ^1 normal
  
  svg ^0.10.0 normal
  
  vcd ^0.6.1 normal
- Versions
- 5.48% of the crate is documented
Platform
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docs.rs
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Rust

rust_hdl0.46.0

In rust_hdl::prelude

Modules

ast
block
clock
logic
probe
sim_time
synth
type_descriptor

Macros

Structs

Enums

Bits
Constraint
OutputBuffer
SDRAMCommand
SignalType
SimError
SlewType
SynthError
Timing
TimingRelative
TimingRelativeEdge
TypeKind
VCDValue
Verilog
WordOrder

Constants

AD7193_REG_WIDTHS
NANOS_PER_FEMTO
SIMULATION_TIME_ONE_SECOND

Traits

Block
HLSNamedPorts
Logic
LogicJoin
LogicLink
Probe
Synth
ToBits
ToSignedBits
VerilogVisitor

Functions

bit_cast
bits
bursty_rand
bursty_vec
check_all
check_connected
check_timing
clog2
filter_blackbox_directives
freq_hz_to_period_femto
generate_verilog
generate_verilog_unchecked
signed
signed_bit_cast
signed_cast
simulate
snore
unsigned_bit_cast
unsigned_cast
write_vcd_change
write_vcd_dump
write_vcd_header
yosys_validate

Type Aliases

Bit
LiteralType

Attribute Macros

hdl_gen

Derive Macros

LogicBlock
LogicInterface
LogicState
LogicStruct

rust_hdl::prelude

Function generate_verilog_unchecked

Settings

Help

pub fn generate_verilog_unchecked<U>(uut: &U) -> Stringwhere
    U: Block,