Struct rust_hdl::prelude::SDRAMFIFO

pub struct SDRAMFIFO<const R: usize, const C: usize, const P: u32, const D: usize, const A: usize> {
    pub clock: Signal<In, Clock>,
    pub sdram: SDRAMDriver<D>,
    pub ram_clock: Signal<In, Clock>,
    pub bus_write: FIFOWriteResponder<Bits<D>>,
    pub bus_read: FIFOReadResponder<Bits<D>>,
    /* private fields */
}

Fields

clock: Signal<In, Clock>

sdram: SDRAMDriver<D>

ram_clock: Signal<In, Clock>

bus_write: FIFOWriteResponder<Bits<D>>

bus_read: FIFOReadResponder<Bits<D>>

Implementations

impl<const R: usize, const C: usize, const P: u32, const D: usize, const A: usize> SDRAMFIFO<R, C, P, D, A>

pub fn new( cas_delay: u32, timings: MemoryTimings, buffer: OutputBuffer ) -> SDRAMFIFO<R, C, P, D, A>

Trait Implementations

impl<const R: usize, const C: usize, const P: u32, const D: usize, const A: usize> Block for SDRAMFIFO<R, C, P, D, A>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const R: usize, const C: usize, const P: u32, const D: usize, const A: usize> Logic for SDRAMFIFO<R, C, P, D, A>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>