Struct rust_hdl::prelude::MOSIWidePort

pub struct MOSIWidePort<const W: usize, const D: usize> {
    pub bus: SoCPortResponder<D>,
    pub clock_out: Signal<Out, Clock>,
    pub port_out: Signal<Out, Bits<W>>,
    pub strobe_out: Signal<Out, bool>,
    /* private fields */
}

Fields

bus: SoCPortResponder<D>

clock_out: Signal<Out, Clock>

port_out: Signal<Out, Bits<W>>

strobe_out: Signal<Out, bool>

Trait Implementations

impl<const W: usize, const D: usize> Block for MOSIWidePort<W, D>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const W: usize, const D: usize> Default for MOSIWidePort<W, D>

fn default() -> MOSIWidePort<W, D>

Returns the “default value” for a type.

impl<const W: usize, const D: usize> Logic for MOSIWidePort<W, D>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>