Struct rust_hdl::prelude::MISOFIFOPort

pub struct MISOFIFOPort<const W: usize, const N: usize, const NP1: usize, const BLOCK: u32> {
    pub bus: SoCPortResponder<W>,
    pub fifo_bus: FIFOWriteResponder<Bits<W>>,
    /* private fields */
}

Fields

bus: SoCPortResponder<W>

fifo_bus: FIFOWriteResponder<Bits<W>>

Trait Implementations

impl<const W: usize, const N: usize, const NP1: usize, const BLOCK: u32> Block for MISOFIFOPort<W, N, NP1, BLOCK>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const W: usize, const N: usize, const NP1: usize, const BLOCK: u32> Default for MISOFIFOPort<W, N, NP1, BLOCK>

fn default() -> MISOFIFOPort<W, N, NP1, BLOCK>

Returns the “default value” for a type.

impl<const W: usize, const N: usize, const NP1: usize, const BLOCK: u32> Logic for MISOFIFOPort<W, N, NP1, BLOCK>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>