Struct rust_hdl::prelude::HLSSPIMuxMasters

pub struct HLSSPIMuxMasters<const D: usize, const A: usize, const N: usize> {
    pub from_masters: [SPIWiresSlave; N],
    pub upstream: SoCBusResponder<D, A>,
    pub to_bus: SPIWiresMaster,
    /* private fields */
}

Fields

from_masters: [SPIWiresSlave; N]

upstream: SoCBusResponder<D, A>

to_bus: SPIWiresMaster

Trait Implementations

impl<const D: usize, const A: usize, const N: usize> Block for HLSSPIMuxMasters<D, A, N>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const D: usize, const A: usize, const N: usize> Default for HLSSPIMuxMasters<D, A, N>

fn default() -> HLSSPIMuxMasters<D, A, N>

Returns the “default value” for a type.

impl<const D: usize, const A: usize, const N: usize> HLSNamedPorts for HLSSPIMuxMasters<D, A, N>

fn ports(&self) -> Vec<String, Global>

impl<const D: usize, const A: usize, const N: usize> Logic for HLSSPIMuxMasters<D, A, N>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>