Struct rust_hdl::prelude::CrossWidenFIFO

pub struct CrossWidenFIFO<const DN: usize, const NN: usize, const NNP1: usize, const DW: usize, const WN: usize, const WNP1: usize> {
    pub data_in: Signal<In, Bits<DN>>,
    pub write: Signal<In, bool>,
    pub full: Signal<Out, bool>,
    pub write_clock: Signal<In, Clock>,
    pub data_out: Signal<Out, Bits<DW>>,
    pub read: Signal<In, bool>,
    pub empty: Signal<Out, bool>,
    pub read_clock: Signal<In, Clock>,
    pub in_fifo: AsynchronousFIFO<Bits<DN>, NN, NNP1, 1>,
    pub out_fifo: SynchronousFIFO<Bits<DW>, WN, WNP1, 1>,
    pub xpand: FIFOExpanderN<DN, DW>,
}

Fields

data_in: Signal<In, Bits<DN>>

write: Signal<In, bool>

full: Signal<Out, bool>

write_clock: Signal<In, Clock>

data_out: Signal<Out, Bits<DW>>

read: Signal<In, bool>

empty: Signal<Out, bool>

read_clock: Signal<In, Clock>

in_fifo: AsynchronousFIFO<Bits<DN>, NN, NNP1, 1>

out_fifo: SynchronousFIFO<Bits<DW>, WN, WNP1, 1>

xpand: FIFOExpanderN<DN, DW>

Implementations

impl<const DN: usize, const NN: usize, const NNP1: usize, const DW: usize, const WN: usize, const WNP1: usize> CrossWidenFIFO<DN, NN, NNP1, DW, WN, WNP1>

pub fn new(order: WordOrder) -> CrossWidenFIFO<DN, NN, NNP1, DW, WN, WNP1>

Trait Implementations

impl<const DN: usize, const NN: usize, const NNP1: usize, const DW: usize, const WN: usize, const WNP1: usize> Block for CrossWidenFIFO<DN, NN, NNP1, DW, WN, WNP1>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const DN: usize, const NN: usize, const NNP1: usize, const DW: usize, const WN: usize, const WNP1: usize> Default for CrossWidenFIFO<DN, NN, NNP1, DW, WN, WNP1>

fn default() -> CrossWidenFIFO<DN, NN, NNP1, DW, WN, WNP1>

Returns the “default value” for a type.

impl<const DN: usize, const NN: usize, const NNP1: usize, const DW: usize, const WN: usize, const WNP1: usize> Logic for CrossWidenFIFO<DN, NN, NNP1, DW, WN, WNP1>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>