Struct rust_hdl::prelude::CrossNarrow

pub struct CrossNarrow<const DW: usize, const WN: usize, const WNP1: usize, const DN: usize, const NN: usize, const NNP1: usize> {
    pub wide_bus: FIFOWriteResponder<Bits<DW>>,
    pub wide_clock: Signal<In, Clock>,
    pub narrow_bus: FIFOReadResponder<Bits<DN>>,
    pub narrow_clock: Signal<In, Clock>,
    /* private fields */
}

Fields

wide_bus: FIFOWriteResponder<Bits<DW>>

wide_clock: Signal<In, Clock>

narrow_bus: FIFOReadResponder<Bits<DN>>

narrow_clock: Signal<In, Clock>

Implementations

impl<const DW: usize, const WN: usize, const WNP1: usize, const DN: usize, const NN: usize, const NNP1: usize> CrossNarrow<DW, WN, WNP1, DN, NN, NNP1>

pub fn new(order: WordOrder) -> CrossNarrow<DW, WN, WNP1, DN, NN, NNP1>

Trait Implementations

impl<const DW: usize, const WN: usize, const WNP1: usize, const DN: usize, const NN: usize, const NNP1: usize> Block for CrossNarrow<DW, WN, WNP1, DN, NN, NNP1>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const DW: usize, const WN: usize, const WNP1: usize, const DN: usize, const NN: usize, const NNP1: usize> Default for CrossNarrow<DW, WN, WNP1, DN, NN, NNP1>

fn default() -> CrossNarrow<DW, WN, WNP1, DN, NN, NNP1>

Returns the “default value” for a type.

impl<const DW: usize, const WN: usize, const WNP1: usize, const DN: usize, const NN: usize, const NNP1: usize> Logic for CrossNarrow<DW, WN, WNP1, DN, NN, NNP1>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>