Struct rust_hdl::prelude::SoCTestChip

pub struct SoCTestChip {
    pub clock: Signal<In, Clock>,
    pub sys_clock: Signal<In, Clock>,
    pub from_cpu: FIFOWriteResponder<Bits<16>>,
    pub to_cpu: FIFOReadResponder<Bits<16>>,
    /* private fields */
}

Fields

clock: Signal<In, Clock>

sys_clock: Signal<In, Clock>

from_cpu: FIFOWriteResponder<Bits<16>>

to_cpu: FIFOReadResponder<Bits<16>>

Trait Implementations

impl Block for SoCTestChip

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl Default for SoCTestChip

fn default() -> SoCTestChip

Returns the “default value” for a type.

impl Logic for SoCTestChip

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>