Struct rust_hdl::prelude::FIFOExpanderN

pub struct FIFOExpanderN<const DN: usize, const DW: usize> {
    pub data_in: Signal<In, Bits<DN>>,
    pub read: Signal<Out, bool>,
    pub empty: Signal<In, bool>,
    pub data_out: Signal<Out, Bits<DW>>,
    pub write: Signal<Out, bool>,
    pub full: Signal<In, bool>,
    pub clock: Signal<In, Clock>,
    /* private fields */
}

Fields

data_in: Signal<In, Bits<DN>>

read: Signal<Out, bool>

empty: Signal<In, bool>

data_out: Signal<Out, Bits<DW>>

write: Signal<Out, bool>

full: Signal<In, bool>

clock: Signal<In, Clock>

Implementations

impl<const DN: usize, const DW: usize> FIFOExpanderN<DN, DW>

pub fn new(order: WordOrder) -> FIFOExpanderN<DN, DW>

Trait Implementations

impl<const DN: usize, const DW: usize> Block for FIFOExpanderN<DN, DW>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const DN: usize, const DW: usize> Logic for FIFOExpanderN<DN, DW>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>