Struct rust_hdl::prelude::ROM

pub struct ROM<D, const N: usize>where
    D: Synth,{
    pub address: Signal<In, Bits<N>>,
    pub data: Signal<Out, D>,
    /* private fields */
}

Fields

address: Signal<In, Bits<N>>

data: Signal<Out, D>

Implementations

impl<D, const N: usize> ROM<D, N>where D: Synth,

pub fn new(values: BTreeMap<Bits<N>, D, Global>) -> ROM<D, N>

Trait Implementations

impl<D, const N: usize> Block for ROM<D, N>where D: Synth,

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<I, D, const N: usize> From<I> for ROM<D, N>where I: Iterator<Item = D>, D: Synth,

fn from(v: I) -> ROM<D, N>

Converts to this type from the input type.

impl<D, const N: usize> Logic for ROM<D, N>where D: Synth,

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo, Global>