Struct rust_hdl::widgets::sdram::SDRAMDevice

pub struct SDRAMDevice<const D: usize> {
    pub clk: Signal<In, Clock>,
    pub we_not: Signal<In, Bit>,
    pub cas_not: Signal<In, Bit>,
    pub ras_not: Signal<In, Bit>,
    pub cs_not: Signal<In, Bit>,
    pub bank: Signal<In, Bits<2>>,
    pub address: Signal<In, Bits<13>>,
    pub write_data: Signal<In, Bits<D>>,
    pub read_data: Signal<Out, Bits<D>>,
    pub write_enable: Signal<In, Bit>,
}

Fields

clk: Signal<In, Clock>

we_not: Signal<In, Bit>

cas_not: Signal<In, Bit>

ras_not: Signal<In, Bit>

cs_not: Signal<In, Bit>

bank: Signal<In, Bits<2>>

address: Signal<In, Bits<13>>

write_data: Signal<In, Bits<D>>

read_data: Signal<Out, Bits<D>>

write_enable: Signal<In, Bit>

Implementations

impl<const D: usize> SDRAMDevice<D>

pub fn join(&mut self, other: &mut SDRAMDriver<D>)

Trait Implementations

impl<const D: usize> Block for SDRAMDevice<D>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const D: usize> Clone for SDRAMDevice<D>

fn clone(&self) -> SDRAMDevice<D>

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<const D: usize> Debug for SDRAMDevice<D>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<const D: usize> Default for SDRAMDevice<D>

fn default() -> SDRAMDevice<D>

Returns the “default value” for a type.

impl<const D: usize> Logic for SDRAMDevice<D>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>

impl<const D: usize> LogicJoin for SDRAMDevice<D>

fn join_connect(&mut self)

fn join_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>

impl<const D: usize> LogicLink for SDRAMDevice<D>

fn link(&mut self, other: &mut Self)

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)

fn link_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>