Struct rust_hdl::hls::host::Host

pub struct Host<const A: usize> {
    pub bidi_bus: BidiBusM<Bits<8>>,
    pub bus: SoCBusController<16, A>,
    pub sys_clock: Signal<In, Clock>,
    pub bidi_clock: Signal<In, Clock>,
    /* private fields */
}

Fields

bidi_bus: BidiBusM<Bits<8>>

bus: SoCBusController<16, A>

sys_clock: Signal<In, Clock>

bidi_clock: Signal<In, Clock>

Implementations

impl<const A: usize> Host<A>

pub fn new(order: WordOrder) -> Self

Trait Implementations

impl<const A: usize> Block for Host<A>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const A: usize> Default for Host<A>

fn default() -> Host<A>

Returns the “default value” for a type.

impl<const A: usize> Logic for Host<A>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>