Struct rust_hdl::widgets::spi::master::SPIWiresSlave

pub struct SPIWiresSlave {
    pub mosi: Signal<In, Bit>,
    pub miso: Signal<Out, Bit>,
    pub msel: Signal<In, Bit>,
    pub mclk: Signal<In, Bit>,
}

Fields

mosi: Signal<In, Bit>

miso: Signal<Out, Bit>

msel: Signal<In, Bit>

mclk: Signal<In, Bit>

Implementations

impl SPIWiresSlave

pub fn join(&mut self, other: &mut SPIWiresMaster)

Trait Implementations

impl Block for SPIWiresSlave

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl Default for SPIWiresSlave

fn default() -> SPIWiresSlave

Returns the “default value” for a type.

impl Logic for SPIWiresSlave

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>

impl LogicJoin for SPIWiresSlave

fn join_connect(&mut self)

fn join_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>

impl LogicLink for SPIWiresSlave

fn link(&mut self, other: &mut Self)

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)

fn link_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>