Struct rust_hdl::hls::expander::Expander

pub struct Expander<const DN: usize, const DW: usize> {
    pub bus_read: FIFOReadController<Bits<DN>>,
    pub bus_write: FIFOWriteController<Bits<DW>>,
    pub clock: Signal<In, Clock>,
    /* private fields */
}

Fields

bus_read: FIFOReadController<Bits<DN>>

bus_write: FIFOWriteController<Bits<DW>>

clock: Signal<In, Clock>

Implementations

impl<const DW: usize, const DN: usize> Expander<DN, DW>

pub fn new(order: WordOrder) -> Self

Trait Implementations

impl<const DN: usize, const DW: usize> Block for Expander<DN, DW>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const DW: usize, const DN: usize> Logic for Expander<DN, DW>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>