Struct rust_hdl::widgets::fifo::fifo_logic::FIFOWriteLogic

pub struct FIFOWriteLogic<D: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> {

    pub write: Signal<In, Bit>,
    pub data_in: Signal<In, D>,
    pub full: Signal<Out, Bit>,
    pub almost_full: Signal<Out, Bit>,
    pub overflow: Signal<Out, Bit>,
    pub clock: Signal<In, Clock>,
    pub ram_write_address: Signal<Out, Bits<N>>,
    pub ram_write_clock: Signal<Out, Clock>,
    pub ram_write_data: Signal<Out, D>,
    pub ram_write_enable: Signal<Out, Bit>,
    pub read_address: Signal<In, Bits<NP1>>,
    pub write_address_delayed: Signal<Out, Bits<NP1>>,
    pub fill_level: Signal<Out, Bits<NP1>>,
    /* private fields */
}

Fields

write: Signal<In, Bit>

data_in: Signal<In, D>

full: Signal<Out, Bit>

almost_full: Signal<Out, Bit>

overflow: Signal<Out, Bit>

clock: Signal<In, Clock>

ram_write_address: Signal<Out, Bits<N>>

ram_write_clock: Signal<Out, Clock>

ram_write_data: Signal<Out, D>

ram_write_enable: Signal<Out, Bit>

read_address: Signal<In, Bits<NP1>>

write_address_delayed: Signal<Out, Bits<NP1>>

fill_level: Signal<Out, Bits<NP1>>

Trait Implementations

impl<D: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Block for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<D: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Default for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE>

fn default() -> Self

Returns the “default value” for a type.

impl<D: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Logic for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>