Trait rust_hdl::core::logic::LogicLink

pub trait LogicLink {
    fn link(&mut self, other: &mut Self);
    fn link_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink> ;
    fn link_connect_source(&mut self);
    fn link_connect_dest(&mut self);
}

Required Methods

fn link(&mut self, other: &mut Self)

fn link_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)

Implementors

impl LogicLink for I2CBusDriver

impl LogicLink for I2CBusReceiver

impl LogicLink for OpenDrainDriver

impl LogicLink for OpenDrainReceiver

impl LogicLink for SPIWiresMaster

impl LogicLink for SPIWiresSlave

impl<D: Synth, const N: usize> LogicLink for RAMWrite<D, N>

impl<T: Synth> LogicLink for BidiBusD<T>

impl<T: Synth> LogicLink for BidiBusM<T>

impl<T: Synth> LogicLink for FIFOReadController<T>

impl<T: Synth> LogicLink for FIFOReadResponder<T>

impl<T: Synth> LogicLink for FIFOWriteController<T>

impl<T: Synth> LogicLink for FIFOWriteResponder<T>

impl<T: Synth> LogicLink for Signal<In, T>

impl<T: Synth> LogicLink for Signal<InOut, T>

impl<T: Synth> LogicLink for Signal<Out, T>

impl<const D: usize> LogicLink for SoCPortController<D>

impl<const D: usize> LogicLink for SoCPortResponder<D>

impl<const D: usize> LogicLink for SDRAMDevice<D>

impl<const D: usize> LogicLink for SDRAMDriver<D>

impl<const D: usize, const A: usize> LogicLink for SoCBusController<D, A>

impl<const D: usize, const A: usize> LogicLink for SoCBusResponder<D, A>