Struct rust_hdl::widgets::spi::slave::SPISlave

pub struct SPISlave<const N: usize> {
    pub clock: Signal<In, Clock>,
    pub wires: SPIWiresSlave,
    pub disabled: Signal<In, Bit>,
    pub busy: Signal<Out, Bit>,
    pub data_inbound: Signal<Out, Bits<N>>,
    pub start_send: Signal<In, Bit>,
    pub data_outbound: Signal<In, Bits<N>>,
    pub bits: Signal<In, Bits<16>>,
    pub continued_transaction: Signal<In, Bit>,
    pub transfer_done: Signal<Out, Bit>,
    /* private fields */
}

The SPISlave is mostly meant for testing the [SPIMaster], but you can use it to implement a SPI endpoint in the FPGA if you want to. This SPISlave is not very robust, so be cautious with using it. In particular, with a very badly behaved SPI master, it may not operate as expected.

Fields

clock: Signal<In, Clock>

The clock driving the SPISlave

wires: SPIWiresSlave

The bus connecting us to the [SPIMaster] or an external SPI bus.

disabled: Signal<In, Bit>

Raise thie disabled signal if you want the SPISlave to ignore the wires signals.

busy: Signal<Out, Bit>

Indicates the SPISlave is busy (typically, receiving data from the [SPIMaster].

data_inbound: Signal<Out, Bits<N>>

Data received from the [SPIMaster] is output on these wires.

start_send: Signal<In, Bit>

Assert for a single cycle to latch the data to be sent back to the [SPIMaster] on the MISO line. Latches data_outbound,bits and continued_transaction when asserted.

data_outbound: Signal<In, Bits<N>>

Data destined for the [SPIMaster] on the next transaction.

bits: Signal<In, Bits<16>>

Number of bits to send. Capped at 16 bits (which corresponds to 64K bits on the send - not realistic).

continued_transaction: Signal<In, Bit>

Set this to true to indicate that the next transaction will be continued from this one (i.e., do not hangup at the end).

transfer_done: Signal<Out, Bit>

A flag that indicates the inbound data is valid.

Implementations

impl<const N: usize> SPISlave<N>

pub fn new(config: SPIConfig) -> Self

Generate a new SPISlave with the given SPIConfig

Arguments

• config: The SPIConfig that configures the slave receiver.

returns: SPISlave<{ N }>

Examples

See [ADS868XSimulator] for an example of how a SPISlave can be used.

Trait Implementations

impl<const N: usize> Block for SPISlave<N>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const N: usize> Logic for SPISlave<N>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>