Struct rust_hdl::hls::bidi::BidiMaster

pub struct BidiMaster<T: Synth> {
    pub bus: BidiBusM<T>,
    pub clock: Signal<In, Clock>,
    pub data_to_bus: FIFOReadController<T>,
    pub data_from_bus: FIFOWriteController<T>,
    /* private fields */
}

Fields

bus: BidiBusM<T>

clock: Signal<In, Clock>

data_to_bus: FIFOReadController<T>

data_from_bus: FIFOWriteController<T>

Trait Implementations

impl<T: Synth> Block for BidiMaster<T>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<T: Default + Synth> Default for BidiMaster<T>

fn default() -> BidiMaster<T>

Returns the “default value” for a type.

impl<T: Synth> Logic for BidiMaster<T>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>