Trait rust_hdl::core::logic::LogicJoin

pub trait LogicJoin {
    fn join_connect(&mut self) { ... }
    fn join_hdl(_my_name: &str, _this: &str, _that: &str) -> Vec<VerilogLink>  { ... }
}

Provided Methods

fn join_connect(&mut self)

fn join_hdl(_my_name: &str, _this: &str, _that: &str) -> Vec<VerilogLink>

Implementors

impl LogicJoin for I2CBusDriver

impl LogicJoin for I2CBusReceiver

impl LogicJoin for OpenDrainDriver

impl LogicJoin for OpenDrainReceiver

impl LogicJoin for SPIWiresMaster

impl LogicJoin for SPIWiresSlave

impl<D: Synth, const N: usize> LogicJoin for RAMWrite<D, N>

impl<T: Synth> LogicJoin for BidiBusD<T>

impl<T: Synth> LogicJoin for BidiBusM<T>

impl<T: Synth> LogicJoin for FIFOReadController<T>

impl<T: Synth> LogicJoin for FIFOReadResponder<T>

impl<T: Synth> LogicJoin for FIFOWriteController<T>

impl<T: Synth> LogicJoin for FIFOWriteResponder<T>

impl<T: Synth> LogicJoin for Signal<In, T>

impl<T: Synth> LogicJoin for Signal<InOut, T>

impl<T: Synth> LogicJoin for Signal<Out, T>

impl<const D: usize> LogicJoin for SoCPortController<D>

impl<const D: usize> LogicJoin for SoCPortResponder<D>

impl<const D: usize> LogicJoin for SDRAMDevice<D>

impl<const D: usize> LogicJoin for SDRAMDriver<D>

impl<const D: usize, const A: usize> LogicJoin for SoCBusController<D, A>

impl<const D: usize, const A: usize> LogicJoin for SoCBusResponder<D, A>