Struct rust_hdl::core::constant::Constant

pub struct Constant<T: Synth> { /* private fields */ }

The Constant wrapper can hold any Synth type and store it in a circuit for use by the HDL kernel. This is the easiest way to compute complex constants in your RustHDL constructors, and then store the results inside the circuit for later use. Unlike [Signal], Constant does not have a .next field, so you cannot assign to a Constant in the HDL kernel (blocked at compile time). Note that Constant does not impl Default. You must construct it with the appropriate value when the circuit is built.

Here is a correct usage of a Constant

 use rust_hdl::prelude::*;

#[derive(LogicBlock)]
struct AddNum {
   pub i1: Signal<In, Bits<8>>,
   pub o1: Signal<Out, Bits<8>>,
   c1: Constant<Bits<8>>,
}

impl Default for AddNum {
    fn default() -> Self {
         Self {
            i1: Default::default(),
            o1: Default::default(),
            c1: Constant::new(42.into()),
         }
    }
}

impl Logic for AddNum {
     #[hdl_gen]
     fn update(&mut self) {
        // Note that `self.c1.next` does not exist... 
        self.o1.next = self.i1.val() + self.c1.val(); 
     }
}

   let mut sim : Simulation<AddNum> = Simulation::default();
   sim.add_testbench(|mut ep: Sim<AddNum>| {
       let mut x = ep.init()?;
       x.i1.next = 13.into();
       x = ep.wait(1, x)?;
       sim_assert_eq!(ep, x.o1.val(), 55, x);
       ep.done(x)
   });
   
   let mut uut = AddNum::default(); uut.connect_all();
   sim.run(Box::new(uut), 100).unwrap();

Implementations

impl<T: Synth> Constant<T>

pub fn new(val: T) -> Constant<T>

Create a new Constant from the given value.

pub fn val(&self) -> T

Retrieve the value of the constant. Usable in HDL kernels.

Trait Implementations

impl<T: Synth> Block for Constant<T>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<T: Clone + Synth> Clone for Constant<T>

fn clone(&self) -> Constant<T>

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<T: Debug + Synth> Debug for Constant<T>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<T: Synth> Logic for Constant<T>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>

impl<T: Copy + Synth> Copy for Constant<T>