Struct rust_hdl::widgets::i2c::i2c_controller::I2CController

pub struct I2CController {
    pub sda: Signal<InOut, Bit>,
    pub scl: Signal<InOut, Bit>,
    pub clock: Signal<In, Clock>,
    pub cmd: Signal<In, I2CControllerCmd>,
    pub run: Signal<In, Bit>,
    pub busy: Signal<Out, Bit>,
    pub error: Signal<Out, Bit>,
    pub write_data_in: Signal<In, Bits<8>>,
    pub read_data_out: Signal<Out, Bits<8>>,
    pub read_valid: Signal<Out, Bit>,
    pub ack: Signal<Out, Bit>,
    pub nack: Signal<Out, Bit>,
    /* private fields */
}

Fields

sda: Signal<InOut, Bit>

scl: Signal<InOut, Bit>

clock: Signal<In, Clock>

cmd: Signal<In, I2CControllerCmd>

run: Signal<In, Bit>

busy: Signal<Out, Bit>

error: Signal<Out, Bit>

write_data_in: Signal<In, Bits<8>>

read_data_out: Signal<Out, Bits<8>>

read_valid: Signal<Out, Bit>

ack: Signal<Out, Bit>

nack: Signal<Out, Bit>

Implementations

impl I2CController

pub fn new(config: I2CConfig) -> Self

Trait Implementations

impl Block for I2CController

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl Logic for I2CController

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>