Struct rust_hdl::core::signal::Signal

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pub struct Signal<D: Direction, T: Synth> {
    pub next: T,
    pub changed: bool,
    /* private fields */
}

Fields

next: Tchanged: bool

Implementations

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impl<T: Synth> Signal<In, T>

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pub fn join(&mut self, other: &mut Signal<Out, T>)

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pub fn join_hdl(
 my_name: &str,
 owner_name: &str,
 other_name: &str
) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

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impl<T: Synth> Signal<Out, T>

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pub fn join(&mut self, other: &mut Signal<In, T>)

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pub fn join_hdl(
 my_name: &str,
 owner_name: &str,
 other_name: &str
) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

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pub fn join_hdl(
 my_name: &str,
 owner_name: &str,
 other_name: &str
) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

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impl<T: Synth> Signal<Local, T>

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pub fn val(&self) -> T

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impl<T: Synth> Signal<In, T>

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pub fn val(&self) -> T

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impl<T: Synth> Signal<Out, T>

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pub fn val(&self) -> T

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impl<T: Synth> Signal<InOut, T>

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pub fn val(&self) -> T

Trait Implementations

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impl<D: Direction, T: Synth> Block for Signal<D, T>

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fn connect_all(&mut self)

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fn update_all(&mut self)

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fn has_changed(&self) -> bool

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fn accept(&self, name: &str, probe: &mut dyn Probe)

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impl<D: Clone + Direction, T: Clone + Synth> Clone for Signal<D, T>

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fn clone(&self) -> Signal<D, T>

Returns a copy of the value. Read more

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fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more

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impl<D: Debug + Direction, T: Debug + Synth> Debug for Signal<D, T>

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fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more

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impl<D: Direction, T: Synth> Default for Signal<D, T>

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fn default() -> Self

Returns the “default value” for a type. Read more

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impl<D: Direction, T: Synth> Logic for Signal<D, T>

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fn update(&mut self)

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fn connect(&mut self)

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fn hdl(&self) -> Verilog

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fn timing(&self) -> Vec<TimingInfo>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

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impl<T: Synth> LogicJoin for Signal<In, T>

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fn join_connect(&mut self)

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fn join_hdl(_my_name: &str, _this: &str, _that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

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impl<T: Synth> LogicJoin for Signal<InOut, T>

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fn join_connect(&mut self)

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fn join_hdl(_my_name: &str, _this: &str, _that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

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impl<T: Synth> LogicJoin for Signal<Out, T>

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fn join_connect(&mut self)

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fn join_hdl(_my_name: &str, _this: &str, _that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

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impl<T: Synth> LogicLink for Signal<In, T>

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fn link(&mut self, other: &mut Self)

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fn link_hdl(my_name: &str, owner_name: &str, other_name: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

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fn link_connect_source(&mut self)

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fn link_connect_dest(&mut self)

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impl<T: Synth> LogicLink for Signal<InOut, T>

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fn link(&mut self, other: &mut Self)

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fn link_hdl(my_name: &str, owner_name: &str, other_name: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

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fn link_connect_source(&mut self)

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fn link_connect_dest(&mut self)

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impl<T: Synth> LogicLink for Signal<Out, T>

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fn link(&mut self, other: &mut Self)

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fn link_hdl(my_name: &str, owner_name: &str, other_name: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

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fn link_connect_source(&mut self)

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fn link_connect_dest(&mut self)

Auto Trait Implementations

impl<D, T> RefUnwindSafe for Signal<D, T> where
D: RefUnwindSafe,
T: RefUnwindSafe,

impl<D, T> Send for Signal<D, T> where
D: Send,
T: Send,

impl<D, T> Sync for Signal<D, T> where
D: Sync,
T: Sync,

impl<D, T> Unpin for Signal<D, T> where
D: Unpin,
T: Unpin,

impl<D, T> UnwindSafe for Signal<D, T> where
D: UnwindSafe,
T: UnwindSafe,

Blanket Implementations

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impl<T> Any for T where
T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more

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impl<T> Borrow<T> for T where
T: ?Sized,

const: unstable · source

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more

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impl<T> BorrowMut<T> for T where
T: ?Sized,

const: unstable · source

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more

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impl<T> From<T> for T

const: unstable · source

fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into for T where
U: From<T>,

const: unstable · source

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

impl<T> Pointable for T

const ALIGN: usize = mem::align_of::<T>()

The alignment of pointer.

type Init = T

The type for initializers.

unsafe fn init(init: <T as Pointable>::Init) -> usize

Initializes a with the given initializer. Read more

unsafe fn deref<'a>(ptr: usize) -> &'a T

Dereferences the given pointer. Read more

unsafe fn deref_mut<'a>(ptr: usize) -> &'a mut T

Mutably dereferences the given pointer. Read more

unsafe fn drop(ptr: usize)

Drops the object pointed to by the given pointer. Read more

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impl<T> ToOwned for T where
T: Clone,

type Owned = T

The resulting type after obtaining ownership.

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fn to_owned(&self) -> T

Creates owned data from borrowed data, usually by cloning. Read more

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fn clone_into(&self, target: &mut T)

Uses borrowed data to replace owned data, usually by cloning. Read more

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impl<T, U> TryFrom for T where
U: Into<T>,

type Error = Infallible

The type returned in the event of a conversion error.

const: unstable · source

fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>

Performs the conversion.

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impl<T, U> TryInto for T where
U: TryFrom<T>,

type Error = >::Error

The type returned in the event of a conversion error.

const: unstable · source

fn try_into(self) -> Result<U, >::Error>

Performs the conversion.

Struct rust_hdl::core::signal::Signal

Fields

Implementations

impl<T: Synth> Signal<In, T>

pub fn join(&mut self, other: &mut Signal<Out, T>)

pub fn join_hdl( my_name: &str, owner_name: &str, other_name: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

impl<T: Synth> Signal<Out, T>

pub fn join(&mut self, other: &mut Signal<In, T>)

pub fn join_hdl( my_name: &str, owner_name: &str, other_name: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

impl<D: Direction, T: Synth> Signal<D, T>

pub fn add_constraint(&mut self, constraint: PinConstraint)

pub fn add_location(&mut self, index: usize, location: &str)

pub fn add_signal_type(&mut self, index: usize, signal: SignalType)

impl Signal<In, Clock>

pub fn pos_edge(&self) -> bool

pub fn neg_edge(&self) -> bool

impl<T: Synth> Signal<Out, T>

pub fn new_with_default(init: T) -> Signal<Out, T>

impl<D: Direction> Signal<D, Bit>

pub fn pin_signal(location: &str, kind: SignalType) -> Signal<D, Bit>

impl<T: Synth> Signal<InOut, T>

pub fn set_tristate_is_output(&mut self, flag: bool)

pub fn is_driving_tristate(&self) -> bool

pub fn simulate_connected_tristate(&mut self, other: &mut Self)

impl<T: Synth> Signal<InOut, T>

pub fn join(&mut self, other: &mut Signal<InOut, T>)

pub fn join_hdl( my_name: &str, owner_name: &str, other_name: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

impl<T: Synth> Signal<Local, T>

pub fn val(&self) -> T

impl<T: Synth> Signal<In, T>

pub fn val(&self) -> T

impl<T: Synth> Signal<Out, T>

pub fn val(&self) -> T

impl<T: Synth> Signal<InOut, T>

pub fn val(&self) -> T

Trait Implementations

impl<D: Direction, T: Synth> Block for Signal<D, T>

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl<D: Clone + Direction, T: Clone + Synth> Clone for Signal<D, T>

fn clone(&self) -> Signal<D, T>

fn clone_from(&mut self, source: &Self)

impl<D: Debug + Direction, T: Debug + Synth> Debug for Signal<D, T>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

impl<D: Direction, T: Synth> Default for Signal<D, T>

fn default() -> Self

impl<D: Direction, T: Synth> Logic for Signal<D, T>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

impl<T: Synth> LogicJoin for Signal<In, T>

fn join_connect(&mut self)

fn join_hdl(_my_name: &str, _this: &str, _that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

impl<T: Synth> LogicJoin for Signal<InOut, T>

fn join_connect(&mut self)

fn join_hdl(_my_name: &str, _this: &str, _that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

impl<T: Synth> LogicJoin for Signal<Out, T>

fn join_connect(&mut self)

fn join_hdl(_my_name: &str, _this: &str, _that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

impl<T: Synth> LogicLink for Signal<In, T>

fn link(&mut self, other: &mut Self)

fn link_hdl(my_name: &str, owner_name: &str, other_name: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)

impl<T: Synth> LogicLink for Signal<InOut, T>

fn link(&mut self, other: &mut Self)

fn link_hdl(my_name: &str, owner_name: &str, other_name: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)

impl<T: Synth> LogicLink for Signal<Out, T>

fn link(&mut self, other: &mut Self)

fn link_hdl(my_name: &str, owner_name: &str, other_name: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)

Auto Trait Implementations

impl<D, T> RefUnwindSafe for Signal<D, T> where D: RefUnwindSafe, T: RefUnwindSafe,

impl<D, T> Send for Signal<D, T> where D: Send, T: Send,

pub fn join_hdl(
my_name: &str,
owner_name: &str,
other_name: &str
) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

pub fn join_hdl(
my_name: &str,
owner_name: &str,
other_name: &str
) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

pub fn join_hdl(
my_name: &str,
owner_name: &str,
other_name: &str
) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

fn timing(&self) -> Vec<TimingInfo>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

fn join_hdl(_my_name: &str, _this: &str, _that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

fn join_hdl(_my_name: &str, _this: &str, _that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

fn join_hdl(_my_name: &str, _this: &str, _that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

fn link_hdl(my_name: &str, owner_name: &str, other_name: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

fn link_hdl(my_name: &str, owner_name: &str, other_name: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

fn link_hdl(my_name: &str, owner_name: &str, other_name: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

impl<D, T> RefUnwindSafe for Signal<D, T> where
D: RefUnwindSafe,
T: RefUnwindSafe,

impl<D, T> Send for Signal<D, T> where
D: Send,
T: Send,

impl<D, T> Sync for Signal<D, T> where
D: Sync,
T: Sync,

impl<D, T> Unpin for Signal<D, T> where
D: Unpin,
T: Unpin,

impl<D, T> UnwindSafe for Signal<D, T> where
D: UnwindSafe,
T: UnwindSafe,

impl<T> Any for T where
T: 'static + ?Sized,

impl<T> Borrow<T> for T where
T: ?Sized,

impl<T> BorrowMut<T> for T where
T: ?Sized,

impl<T, U> Into<U> for T where
U: From<T>,

impl<T> ToOwned for T where
T: Clone,

impl<T, U> TryFrom<U> for T where
U: Into<T>,

impl<T, U> TryInto<U> for T where
U: TryFrom<T>,

impl<V, T> VZip<V> for T where
V: MultiLane<T>,