Struct rust_hdl::widgets::sdram::SDRAMDriver

source · [−]

pub struct SDRAMDriver<const D: usize> {
    pub clk: Signal<Out, Clock>,
    pub we_not: Signal<Out, Bit>,
    pub cas_not: Signal<Out, Bit>,
    pub ras_not: Signal<Out, Bit>,
    pub cs_not: Signal<Out, Bit>,
    pub bank: Signal<Out, Bits<2>>,
    pub address: Signal<Out, Bits<13>>,
    pub write_data: Signal<Out, Bits<D>>,
    pub read_data: Signal<In, Bits<D>>,
    pub write_enable: Signal<Out, Bit>,
}

Fields

clk: Signal<Out, Clock>we_not: Signal<Out, Bit>cas_not: Signal<Out, Bit>ras_not: Signal<Out, Bit>cs_not: Signal<Out, Bit>bank: Signal<Out, Bits<2>>address: Signal<Out, Bits<13>>write_data: Signal<Out, Bits<D>>read_data: Signal<In, Bits<D>>write_enable: Signal<Out, Bit>

Struct rust_hdl::widgets::sdram::SDRAMDriver

Fields

Implementations

impl<const D: usize> SDRAMDriver<D>

pub fn join(&mut self, other: &mut SDRAMDevice<D>)

Trait Implementations

impl<const D: usize> Block for SDRAMDriver<D>

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl<const D: usize> Clone for SDRAMDriver<D>

fn clone(&self) -> SDRAMDriver<D>

fn clone_from(&mut self, source: &Self)

impl<const D: usize> Debug for SDRAMDriver<D>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

impl<const D: usize> Default for SDRAMDriver<D>

fn default() -> SDRAMDriver<D>

impl<const D: usize> Logic for SDRAMDriver<D>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

impl<const D: usize> LogicJoin for SDRAMDriver<D>

fn join_connect(&mut self)

fn join_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

impl<const D: usize> LogicLink for SDRAMDriver<D>

fn link(&mut self, other: &mut Self)

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)

fn link_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

Auto Trait Implementations

impl<const D: usize> RefUnwindSafe for SDRAMDriver<D>

impl<const D: usize> Send for SDRAMDriver<D>

impl<const D: usize> Sync for SDRAMDriver<D>

impl<const D: usize> Unpin for SDRAMDriver<D>

impl<const D: usize> UnwindSafe for SDRAMDriver<D>

Blanket Implementations

impl<T> Any for T where T: 'static + ?Sized,

fn type_id(&self) -> TypeId

impl<T> Borrow<T> for T where T: ?Sized,

fn borrow(&self) -> &T

impl<T> BorrowMut<T> for T where T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

fn from(t: T) -> T

impl<T, U> Into<U> for T where U: From<T>,

fn into(self) -> U

impl<T> Pointable for T

const ALIGN: usize = mem::align_of::<T>()

type Init = T

unsafe fn init(init: <T as Pointable>::Init) -> usize

unsafe fn deref<'a>(ptr: usize) -> &'a T

unsafe fn deref_mut<'a>(ptr: usize) -> &'a mut T

unsafe fn drop(ptr: usize)

impl<T> ToOwned for T where T: Clone,

type Owned = T

fn to_owned(&self) -> T

fn clone_into(&self, target: &mut T)

impl<T, U> TryFrom<U> for T where U: Into<T>,

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for T where U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

impl<V, T> VZip<V> for T where V: MultiLane<T>,

fn vzip(self) -> V

fn timing(&self) -> Vec<TimingInfo>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

fn join_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

fn link_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

impl<T> Any for T where
T: 'static + ?Sized,

impl<T> Borrow<T> for T where
T: ?Sized,

impl<T> BorrowMut<T> for T where
T: ?Sized,

impl<T, U> Into<U> for T where
U: From<T>,

impl<T> ToOwned for T where
T: Clone,

impl<T, U> TryFrom<U> for T where
U: Into<T>,

impl<T, U> TryInto<U> for T where
U: TryFrom<T>,

impl<V, T> VZip<V> for T where
V: MultiLane<T>,