Struct rust_hdl::sim::sdr_sdram::bank::MemoryBank

pub struct MemoryBank<const R: usize, const C: usize, const A: usize, const D: usize> {
    pub clock: Signal<In, Clock>,
    pub cas_delay: Signal<In, Bits<3>>,
    pub write_burst: Signal<In, Bit>,
    pub address: Signal<In, Bits<13>>,
    pub burst_len: Signal<In, Bits<4>>,
    pub cmd: Signal<In, SDRAMCommand>,
    pub error: Signal<Out, Bit>,
    pub busy: Signal<Out, Bit>,
    pub write_data: Signal<In, Bits<D>>,
    pub read_data: Signal<Out, Bits<D>>,
    pub read_valid: Signal<Out, Bit>,
    pub select: Signal<In, Bit>,
    /* private fields */
}

Fields

clock: Signal<In, Clock>

cas_delay: Signal<In, Bits<3>>

write_burst: Signal<In, Bit>

address: Signal<In, Bits<13>>

burst_len: Signal<In, Bits<4>>

cmd: Signal<In, SDRAMCommand>

error: Signal<Out, Bit>

busy: Signal<Out, Bit>

write_data: Signal<In, Bits<D>>

read_data: Signal<Out, Bits<D>>

read_valid: Signal<Out, Bit>

select: Signal<In, Bit>

Implementations

impl<const R: usize, const C: usize, const A: usize, const D: usize> MemoryBank<R, C, A, D>

pub fn new(timings: MemoryTimings) -> Self

Trait Implementations

impl<const R: usize, const C: usize, const A: usize, const D: usize> Block for MemoryBank<R, C, A, D>

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl<const R: usize, const C: usize, const A: usize, const D: usize> Logic for MemoryBank<R, C, A, D>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>