Struct rust_hdl::widgets::tristate::TristateBuffer

pub struct TristateBuffer<D: Synth> {
    pub bus: Signal<InOut, D>,
    pub write_enable: Signal<In, Bit>,
    pub write_data: Signal<In, D>,
    pub read_data: Signal<Out, D>,
}

Tristate Buffer

Most FPGAs do not support internal tristate logic. Instead, the compilers turn tristate logic into a combination of a pair of signals (one in, one out) and an enable line. However, the real world definitely needs tristate logic, and there are usually dedicated buffers on the FPGA that can drive a tristate line using a pin that is appropriately configured.

Most FPGA toolchains can infer the tristate buffer when it’s at the edge of the design. So when you need a tristate buffer, you can use this struct. Note that it is generic over the signals being tristated. So you can include a set of different tristate buffers with a single entity.

// An example of a simple tristate 8-bit bus
#[derive(LogicInterface, Default)]
struct EightBitBus {
   bus: Signal<InOut, Bits<8>>,
}

Fields

bus: Signal<InOut, D>

The tristated signals come out of this pin. This should be a top level signal in your design.

write_enable: Signal<In, Bit>

When asserted (true), the bus will attempt to drive write_data to the pins.

write_data: Signal<In, D>

The data to write to the bus. Ignored when write_enable is not active (high).

read_data: Signal<Out, D>

The read back from the bus. When write_enable is false, then this signal represents the external signals driving the FPGA pins. For FPGA, this is likely equal to write_data when write_enable is true.

Trait Implementations

impl<D: Synth> Block for TristateBuffer<D>

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl<D: Default + Synth> Default for TristateBuffer<D>

fn default() -> TristateBuffer<D>

Returns the “default value” for a type.

impl<D: Synth> Logic for TristateBuffer<D>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>