Struct rust_hdl::widgets::spi::master::SPIWiresMaster

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pub struct SPIWiresMaster {
    pub mosi: Signal<Out, Bit>,
    pub miso: Signal<In, Bit>,
    pub msel: Signal<Out, Bit>,
    pub mclk: Signal<Out, Bit>,
}

Fields

mosi: Signal<Out, Bit>miso: Signal<In, Bit>msel: Signal<Out, Bit>mclk: Signal<Out, Bit>

Implementations

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impl SPIWiresMaster

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pub fn join(&mut self, other: &mut SPIWiresSlave)

Trait Implementations

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fn default() -> SPIWiresMaster

Returns the “default value” for a type. Read more

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impl Logic for SPIWiresMaster

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fn update(&mut self)

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fn connect(&mut self)

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fn hdl(&self) -> Verilog

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fn timing(&self) -> Vec<TimingInfo>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

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impl LogicJoin for SPIWiresMaster

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fn join_connect(&mut self)

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fn join_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

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impl LogicLink for SPIWiresMaster

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fn link(&mut self, other: &mut Self)

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fn link_connect_source(&mut self)

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fn link_connect_dest(&mut self)

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fn link_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

Auto Trait Implementations

impl RefUnwindSafe for SPIWiresMaster

impl Send for SPIWiresMaster

impl Sync for SPIWiresMaster

impl Unpin for SPIWiresMaster

impl UnwindSafe for SPIWiresMaster

Blanket Implementations

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impl<T> Any for T where
T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more

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impl<T> Borrow<T> for T where
T: ?Sized,

const: unstable · source

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more

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impl<T> BorrowMut<T> for T where
T: ?Sized,

const: unstable · source

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more

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impl<T> From<T> for T

const: unstable · source

fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into for T where
U: From<T>,

const: unstable · source

fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

impl<T> Pointable for T

const ALIGN: usize = mem::align_of::<T>()

The alignment of pointer.

type Init = T

The type for initializers.

unsafe fn init(init: <T as Pointable>::Init) -> usize

Initializes a with the given initializer. Read more

unsafe fn deref<'a>(ptr: usize) -> &'a T

Dereferences the given pointer. Read more

unsafe fn deref_mut<'a>(ptr: usize) -> &'a mut T

Mutably dereferences the given pointer. Read more

unsafe fn drop(ptr: usize)

Drops the object pointed to by the given pointer. Read more

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impl<T, U> TryFrom for T where
U: Into<T>,

type Error = Infallible

The type returned in the event of a conversion error.

const: unstable · source

fn try_from(value: U) -> Result<T, <T as TryFrom>::Error>

Performs the conversion.

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impl<T, U> TryInto for T where
U: TryFrom<T>,

type Error = >::Error

The type returned in the event of a conversion error.

const: unstable · source

fn try_into(self) -> Result<U, >::Error>

Performs the conversion.

Struct rust_hdl::widgets::spi::master::SPIWiresMaster

Fields

Implementations

impl SPIWiresMaster

pub fn join(&mut self, other: &mut SPIWiresSlave)

Trait Implementations

impl Block for SPIWiresMaster

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl Default for SPIWiresMaster

fn default() -> SPIWiresMaster

impl Logic for SPIWiresMaster

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

impl LogicJoin for SPIWiresMaster

fn join_connect(&mut self)

fn join_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

impl LogicLink for SPIWiresMaster

fn link(&mut self, other: &mut Self)

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)

fn link_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

Auto Trait Implementations

impl RefUnwindSafe for SPIWiresMaster

impl Send for SPIWiresMaster

impl Sync for SPIWiresMaster

impl Unpin for SPIWiresMaster

impl UnwindSafe for SPIWiresMaster

Blanket Implementations

impl<T> Any for T where T: 'static + ?Sized,

fn type_id(&self) -> TypeId

impl<T> Borrow<T> for T where T: ?Sized,

fn borrow(&self) -> &T

impl<T> BorrowMut<T> for T where T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

fn from(t: T) -> T

impl<T, U> Into<U> for T where U: From<T>,

fn into(self) -> U

impl<T> Pointable for T

const ALIGN: usize = mem::align_of::<T>()

type Init = T

unsafe fn init(init: <T as Pointable>::Init) -> usize

unsafe fn deref<'a>(ptr: usize) -> &'a T

unsafe fn deref_mut<'a>(ptr: usize) -> &'a mut T

unsafe fn drop(ptr: usize)

impl<T, U> TryFrom<U> for T where U: Into<T>,

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for T where U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

impl<V, T> VZip<V> for T where V: MultiLane<T>,

fn vzip(self) -> V

fn timing(&self) -> Vec<TimingInfo>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

fn join_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

fn link_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

impl<T> Any for T where
T: 'static + ?Sized,

impl<T> Borrow<T> for T where
T: ?Sized,

impl<T> BorrowMut<T> for T where
T: ?Sized,

impl<T, U> Into<U> for T where
U: From<T>,

impl<T, U> TryFrom<U> for T where
U: Into<T>,

impl<T, U> TryInto<U> for T where
U: TryFrom<T>,

impl<V, T> VZip<V> for T where
V: MultiLane<T>,