List of all items

Structs

• core::ast::BlackBox
• core::ast::Wrapper
• core::check_error::LogicLoop
• core::check_error::OpenConnection
• core::check_logic_loops::VerilogLogicLoopDetector
• core::check_timing::SignalGraph
• core::check_timing::SignalNode
• core::check_timing::TimingChecker
• core::clock::Clock
• core::code_writer::CodeWriter
• core::constant::Constant
• core::constraint::FalsePathRegexp
• core::constraint::InputTimingConstraint
• core::constraint::OutputTimingConstraint
• core::constraint::PeriodicTiming
• core::constraint::PinConstraint
• core::constraint::VivadoInputTimingConstraint
• core::constraint::VivadoOutputTimingConstraint
• core::direction::In
• core::direction::InOut
• core::direction::Local
• core::direction::Out
• core::module_defines::ModuleDefines
• core::named_path::NamedPath
• core::signal::Signal
• core::signed::Signed
• core::simulate::Sim
• core::simulate::Simulation
• core::timing::TimingInfo
• core::type_descriptor::TypeDescriptor
• core::type_descriptor::TypeField
• core::vcd_probe::VCDProbe
• core::verilog_gen::VerilogCodeGenerator
• core::yosys::TopWrap
• docs::BlinkyExample
• docs::vcd2svg::display_metrics::DisplayMetrics
• docs::vcd2svg::trace_collection::TraceCollection
• docs::vcd2svg::vcd_style::VCDStyle
• hls::bidi::BidiBusD
• hls::bidi::BidiBusM
• hls::bidi::BidiMaster
• hls::bidi::BidiSimulatedDevice
• hls::bridge::Bridge
• hls::bus::FIFOReadController
• hls::bus::FIFOReadResponder
• hls::bus::FIFOWriteController
• hls::bus::FIFOWriteResponder
• hls::bus::SoCBusController
• hls::bus::SoCBusResponder
• hls::bus::SoCPortController
• hls::bus::SoCPortResponder
• hls::controller::BaseController
• hls::cross_fifo::CrossNarrow
• hls::cross_fifo::CrossWiden
• hls::expander::Expander
• hls::fifo::AsyncFIFO
• hls::fifo::SyncFIFO
• hls::fifo_linker::FIFOLink
• hls::host::Host
• hls::miso_fifo_port::MISOFIFOPort
• hls::miso_port::MISOPort
• hls::miso_wide_port::MISOWidePort
• hls::mosi_fifo_port::MOSIFIFOPort
• hls::mosi_port::MOSIPort
• hls::mosi_wide_port::MOSIWidePort
• hls::reducer::Reducer
• hls::router::Router
• hls::router_rom::RouterROM
• hls::sdram_controller::SDRAMController
• hls::sdram_controller_tester::SDRAMControllerTester
• hls::sdram_fifo::SDRAMFIFO
• hls::spi::HLSSPIMaster
• hls::spi::HLSSPIMasterDynamicMode
• hls::spi::HLSSPIMuxMasters
• hls::spi::HLSSPIMuxSlaves
• sim::ad7193_sim::AD7193Config
• sim::ad7193_sim::AD7193Simulator
• sim::ads868x_sim::ADS868XSimulator
• sim::max31856_sim::MAX31856Simulator
• sim::muxed_ad7193_sim::MuxedAD7193Simulators
• sim::muxed_ads868x_sim::MuxedADS868XSimulators
• sim::muxed_max31856_sim::MuxedMAX31856Simulators
• sim::sdr_sdram::bank::MemoryBank
• sim::sdr_sdram::chip::SDRAMSimulator
• widgets::accum::Accum
• widgets::auto_reset::AutoReset
• widgets::delay_line::DelayLine
• widgets::dff::DFF
• widgets::dff_with_init::DFFWithInit
• widgets::edge_detector::EdgeDetector
• widgets::edge_ff::EdgeDFF
• widgets::fifo::async_fifo::AsynchronousFIFO
• widgets::fifo::cross_fifo::CrossNarrowFIFO
• widgets::fifo::cross_fifo::CrossWidenFIFO
• widgets::fifo::fifo_expander_n::FIFOExpanderN
• widgets::fifo::fifo_logic::FIFOReadLogic
• widgets::fifo::fifo_logic::FIFOWriteLogic
• widgets::fifo::fifo_reducer::FIFOReducer
• widgets::fifo::fifo_reducer_n::FIFOReducerN
• widgets::fifo::fifo_register::RegisterFIFO
• widgets::fifo::sync_fifo::SynchronousFIFO
• widgets::i2c::i2c_controller::I2CController
• widgets::i2c::i2c_driver::I2CConfig
• widgets::i2c::i2c_driver::I2CDriver
• widgets::i2c::i2c_target::I2CTarget
• widgets::i2c::i2c_test_target::I2CTestTarget
• widgets::mac_fir::MultiplyAccumulateSymmetricFiniteImpulseResponseFilter
• widgets::open_drain::OpenDrainBuffer
• widgets::png::lfsr::LFSRSimple
• widgets::pulser::Pulser
• widgets::pwm::PulseWidthModulator
• widgets::ramrom::ram::RAM
• widgets::ramrom::ram::RAMWrite
• widgets::ramrom::rom::ROM
• widgets::ramrom::sync_rom::SyncROM
• widgets::registered_edge_tristate::RegisteredEdgeTristate
• widgets::sdram::SDRAMDevice
• widgets::sdram::SDRAMDriver
• widgets::sdram::basic_controller::SDRAMBaseController
• widgets::sdram::buffer::SDRAMOnChipBuffer
• widgets::sdram::burst_controller::SDRAMBurstController
• widgets::sdram::cmd::SDRAMCommandDecoder
• widgets::sdram::cmd::SDRAMCommandEncoder
• widgets::sdram::fifo_sdram::SDRAMFIFOController
• widgets::sdram::timings::MemoryTimings
• widgets::shot::Shot
• widgets::spi::master::SPIConfig
• widgets::spi::master::SPIMaster
• widgets::spi::master::SPIWiresMaster
• widgets::spi::master::SPIWiresSlave
• widgets::spi::master_dynamic_mode::SPIConfigDynamicMode
• widgets::spi::master_dynamic_mode::SPIMasterDynamicMode
• widgets::spi::mux::MuxMasters
• widgets::spi::mux::MuxSlaves
• widgets::spi::slave::SPISlave
• widgets::strobe::Strobe
• widgets::synchronizer::BitSynchronizer
• widgets::synchronizer::SyncReceiver
• widgets::synchronizer::SyncSender
• widgets::synchronizer::VectorSynchronizer
• widgets::test_helpers::FaderWithSyncROM
• widgets::test_helpers::LazyFIFOFeeder
• widgets::test_helpers::LazyFIFOReader
• widgets::test_helpers::SoCTestChip
• widgets::tristate::TristateBuffer

Enums

• core::ast::Verilog
• core::bits::Bits
• core::check_error::CheckError
• core::check_timing::ExpressionMode
• core::check_timing::SignalEdgeKind
• core::check_timing::SignalNodeKind
• core::constraint::Constraint
• core::constraint::SignalType
• core::constraint::SlewType
• core::constraint::Timing
• core::constraint::TimingRelative
• core::constraint::TimingRelativeEdge
• core::simulate::SimError
• core::synth::VCDValue
• core::type_descriptor::TypeKind
• core::yosys::SynthError
• sim::sdr_sdram::bank::BankState
• widgets::fifo::fifo_expander_n::WordOrder
• widgets::i2c::i2c_controller::I2CControllerCmd
• widgets::i2c::i2c_driver::I2CDriverCmd
• widgets::sdram::OutputBuffer
• widgets::sdram::cmd::SDRAMCommand

Traits

• core::bits::ToBits
• core::block::Block
• core::direction::Direction
• core::logic::Logic
• core::logic::LogicJoin
• core::logic::LogicLink
• core::probe::Probe
• core::signed::ToSignedBits
• core::synth::Synth
• core::verilog_visitor::VerilogVisitor
• hls::HLSNamedPorts

Macros

• bus_address_strobe
• bus_write_strobe
• clock
• declare_async_fifo
• declare_expanding_fifo
• declare_narrowing_fifo
• declare_sync_fifo
• dff_setup
• hls_fifo_read
• hls_fifo_read_lazy
• hls_fifo_write
• hls_fifo_write_lazy
• hls_host_drain
• hls_host_get_word
• hls_host_get_words
• hls_host_issue_read
• hls_host_noop
• hls_host_ping
• hls_host_put_word
• hls_host_write
• i2c_begin_read
• i2c_begin_write
• i2c_end_transmission
• i2c_read
• i2c_read_last
• i2c_write
• sdram_activate
• sdram_boot
• sdram_cmd
• sdram_precharge_one
• sdram_read
• sdram_reada
• sdram_refresh
• sdram_write
• sim_assert
• sim_assert_eq
• simple_sim
• target_path
• vcd_path
• wait_clock_cycle
• wait_clock_cycles
• wait_clock_false
• wait_clock_true

Attribute Macros

• core::prelude::hdl_gen

Derive Macros

• core::prelude::LogicBlock
• core::prelude::LogicInterface
• core::prelude::LogicState
• core::prelude::LogicStruct

Functions

• core::bits::bit_cast
• core::bits::bits
• core::bits::clog2
• core::check_connected::check_connected
• core::check_error::check_all
• core::check_logic_loops::check_logic_loops
• core::check_timing::check_timing
• core::clock::freq_hz_to_period_femto
• core::logic::logic_connect_fn
• core::logic::logic_connect_join_fn
• core::logic::logic_connect_link_fn
• core::module_defines::generate_verilog
• core::module_defines::generate_verilog_unchecked
• core::signal::get_signal_id
• core::signed::signed
• core::signed::signed_bit_cast
• core::signed::signed_cast
• core::signed::unsigned_bit_cast
• core::signed::unsigned_cast
• core::simulate::simulate
• core::vcd_probe::write_vcd_change
• core::vcd_probe::write_vcd_dump
• core::vcd_probe::write_vcd_header
• core::verilog_gen::filter_blackbox_directives
• core::verilog_gen::verilog_combinatorial
• core::verilog_gen::verilog_link_extraction
• core::verilog_visitor::walk_assignment
• core::verilog_visitor::walk_binop
• core::verilog_visitor::walk_block
• core::verilog_visitor::walk_block_or_conditional
• core::verilog_visitor::walk_case
• core::verilog_visitor::walk_cast
• core::verilog_visitor::walk_conditional
• core::verilog_visitor::walk_expression
• core::verilog_visitor::walk_index
• core::verilog_visitor::walk_index_assignment
• core::verilog_visitor::walk_index_replacement
• core::verilog_visitor::walk_lhs_expression
• core::verilog_visitor::walk_loop
• core::verilog_visitor::walk_match
• core::verilog_visitor::walk_paren
• core::verilog_visitor::walk_slice
• core::verilog_visitor::walk_slice_assignment
• core::verilog_visitor::walk_slice_replace
• core::verilog_visitor::walk_statement
• core::verilog_visitor::walk_unop
• core::yosys::yosys_validate
• docs::vcd2svg::vcd_to_svg
• widgets::ramrom::rom::make_btree_from_iterable
• widgets::sdram::timings::nanos_to_clocks
• widgets::test_helpers::bursty_rand
• widgets::test_helpers::bursty_vec
• widgets::test_helpers::snore

Typedefs

• core::bits::Bit
• core::bits::LiteralType
• core::check_error::LoopMap
• core::check_error::OpenMap
• core::signed::SignedLiteralType
• core::simulate::CustomLogicFn
• core::simulate::Result

Constants

• core::bits::LITERAL_BITS
• core::clock::NANOS_PER_FEMTO
• core::signed::SIGNED_LITERAL_BITS
• core::simulate::SIMULATION_TIME_ONE_SECOND
• sim::ad7193_sim::AD7193_REG_WIDTHS