Struct rust_hdl::widgets::fifo::fifo_logic::FIFOWriteLogic

source · [−]

pub struct FIFOWriteLogic<D: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> {Show 13 fields
    pub write: Signal<In, Bit>,
    pub data_in: Signal<In, D>,
    pub full: Signal<Out, Bit>,
    pub almost_full: Signal<Out, Bit>,
    pub overflow: Signal<Out, Bit>,
    pub clock: Signal<In, Clock>,
    pub ram_write_address: Signal<Out, Bits<N>>,
    pub ram_write_clock: Signal<Out, Clock>,
    pub ram_write_data: Signal<Out, D>,
    pub ram_write_enable: Signal<Out, Bit>,
    pub read_address: Signal<In, Bits<NP1>>,
    pub write_address_delayed: Signal<Out, Bits<NP1>>,
    pub fill_level: Signal<Out, Bits<NP1>>,
    /* private fields */
}

Fields

write: Signal<In, Bit>data_in: Signal<In, D>full: Signal<Out, Bit>almost_full: Signal<Out, Bit>overflow: Signal<Out, Bit>clock: Signal<In, Clock>ram_write_address: Signal<Out, Bits<N>>ram_write_clock: Signal<Out, Clock>ram_write_data: Signal<Out, D>ram_write_enable: Signal<Out, Bit>read_address: Signal<In, Bits<NP1>>write_address_delayed: Signal<Out, Bits<NP1>>fill_level: Signal<Out, Bits<NP1>>

Struct rust_hdl::widgets::fifo::fifo_logic::FIFOWriteLogic

Fields

Trait Implementations

impl<D: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Block for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE>

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl<D: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Default for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE>

fn default() -> Self

impl<D: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Logic for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>ⓘNotable traits for Vec<u8, A>impl<A> Write for Vec<u8, A> where A: Allocator,

Auto Trait Implementations

impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> RefUnwindSafe for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE> where D: RefUnwindSafe,

impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Send for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE> where D: Send,

impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Sync for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE> where D: Sync,

impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Unpin for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE> where D: Unpin,

impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> UnwindSafe for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE> where D: UnwindSafe,

Blanket Implementations

impl<T> Any for T where T: 'static + ?Sized,

fn type_id(&self) -> TypeId

impl<T> Borrow<T> for T where T: ?Sized,

fn borrow(&self) -> &T

impl<T> BorrowMut<T> for T where T: ?Sized,

fn borrow_mut(&mut self) -> &mut T

impl<T> From<T> for T

fn from(t: T) -> T

impl<T, U> Into<U> for T where U: From<T>,

fn into(self) -> U

impl<T> Pointable for T

const ALIGN: usize = mem::align_of::<T>()

type Init = T

unsafe fn init(init: <T as Pointable>::Init) -> usize

unsafe fn deref<'a>(ptr: usize) -> &'a T

unsafe fn deref_mut<'a>(ptr: usize) -> &'a mut T

unsafe fn drop(ptr: usize)

impl<T, U> TryFrom<U> for T where U: Into<T>,

type Error = Infallible

fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

impl<T, U> TryInto<U> for T where U: TryFrom<T>,

type Error = <U as TryFrom<T>>::Error

fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

impl<V, T> VZip<V> for T where V: MultiLane<T>,

fn vzip(self) -> V

fn timing(&self) -> Vec<TimingInfo>ⓘNotable traits for Vec<u8, A>`impl<A> Write for Vec<u8, A> where A: Allocator,`

impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> RefUnwindSafe for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE> where
D: RefUnwindSafe,

impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Send for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE> where
D: Send,

impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Sync for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE> where
D: Sync,

impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Unpin for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE> where
D: Unpin,

impl<D, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> UnwindSafe for FIFOWriteLogic<D, N, NP1, BLOCK_SIZE> where
D: UnwindSafe,

impl<T> Any for T where
T: 'static + ?Sized,

impl<T> Borrow<T> for T where
T: ?Sized,

impl<T> BorrowMut<T> for T where
T: ?Sized,

impl<T, U> Into<U> for T where
U: From<T>,

impl<T, U> TryFrom<U> for T where
U: Into<T>,

impl<T, U> TryInto<U> for T where
U: TryFrom<T>,

impl<V, T> VZip<V> for T where
V: MultiLane<T>,