Struct rust_hdl::hls::bus::SoCPortController

pub struct SoCPortController<const D: usize> {
    pub select: Signal<Out, Bit>,
    pub from_controller: Signal<Out, Bits<D>>,
    pub to_controller: Signal<In, Bits<D>>,
    pub ready: Signal<In, Bit>,
    pub strobe: Signal<Out, Bit>,
    pub clock: Signal<Out, Clock>,
}

Fields

select: Signal<Out, Bit>

from_controller: Signal<Out, Bits<D>>

to_controller: Signal<In, Bits<D>>

ready: Signal<In, Bit>

strobe: Signal<Out, Bit>

clock: Signal<Out, Clock>

Implementations

impl<const D: usize> SoCPortController<D>

pub fn join(&mut self, other: &mut SoCPortResponder<D>)

Trait Implementations

impl<const D: usize> Block for SoCPortController<D>

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl<const D: usize> Clone for SoCPortController<D>

fn clone(&self) -> SoCPortController<D>

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<const D: usize> Debug for SoCPortController<D>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<const D: usize> Default for SoCPortController<D>

fn default() -> SoCPortController<D>

Returns the “default value” for a type.

impl<const D: usize> Logic for SoCPortController<D>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>

impl<const D: usize> LogicJoin for SoCPortController<D>

fn join_connect(&mut self)

fn join_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>

impl<const D: usize> LogicLink for SoCPortController<D>

fn link(&mut self, other: &mut Self)

fn link_connect_source(&mut self)

fn link_connect_dest(&mut self)

fn link_hdl(my_name: &str, this: &str, that: &str) -> Vec<VerilogLink>