Struct rust_hdl::sim::ads868x_sim::ADS868XSimulator

pub struct ADS868XSimulator {
    pub wires: SPIWiresSlave,
    pub clock: Signal<In, Clock>,
    /* private fields */
}

Fields

wires: SPIWiresSlave

clock: Signal<In, Clock>

Implementations

impl ADS868XSimulator

pub fn spi_hw() -> SPIConfig

pub fn spi_sw() -> SPIConfig

pub fn new(spi_config: SPIConfig) -> Self

Trait Implementations

impl Block for ADS868XSimulator

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl Logic for ADS868XSimulator

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>