Struct rust_hdl::widgets::sdram::fifo_sdram::SDRAMFIFOController

pub struct SDRAMFIFOController<const R: usize, const C: usize, const L: u32, const D: usize, const A: usize> {
    pub clock: Signal<In, Clock>,
    pub sdram: SDRAMDriver<D>,
    pub ram_clock: Signal<In, Clock>,
    pub data_in: Signal<In, Bits<D>>,
    pub write: Signal<In, Bit>,
    pub full: Signal<Out, Bit>,
    pub data_out: Signal<Out, Bits<D>>,
    pub read: Signal<In, Bit>,
    pub empty: Signal<Out, Bit>,
    pub overflow: Signal<Out, Bit>,
    pub underflow: Signal<Out, Bit>,
    pub status: Signal<Out, Bits<8>>,
    /* private fields */
}

Fields

clock: Signal<In, Clock>

sdram: SDRAMDriver<D>

ram_clock: Signal<In, Clock>

data_in: Signal<In, Bits<D>>

write: Signal<In, Bit>

full: Signal<Out, Bit>

data_out: Signal<Out, Bits<D>>

read: Signal<In, Bit>

empty: Signal<Out, Bit>

overflow: Signal<Out, Bit>

underflow: Signal<Out, Bit>

status: Signal<Out, Bits<8>>

Implementations

impl<const R: usize, const C: usize, const L: u32, const D: usize, const A: usize> SDRAMFIFOController<R, C, L, D, A>

pub fn new(cas_delay: u32, timings: MemoryTimings, buffer: OutputBuffer) -> Self

Trait Implementations

impl<const R: usize, const C: usize, const L: u32, const D: usize, const A: usize> Block for SDRAMFIFOController<R, C, L, D, A>

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl<const R: usize, const C: usize, const L: u32, const D: usize, const A: usize> Logic for SDRAMFIFOController<R, C, L, D, A>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>