Struct rust_hdl::widgets::spi::master::SPIMaster

pub struct SPIMaster<const N: usize> {
    pub clock: Signal<In, Clock>,
    pub bits_outbound: Signal<In, Bits<16>>,
    pub data_outbound: Signal<In, Bits<N>>,
    pub data_inbound: Signal<Out, Bits<N>>,
    pub start_send: Signal<In, Bit>,
    pub transfer_done: Signal<Out, Bit>,
    pub continued_transaction: Signal<In, Bit>,
    pub busy: Signal<Out, Bit>,
    pub wires: SPIWiresMaster,
    /* private fields */
}

Fields

clock: Signal<In, Clock>

bits_outbound: Signal<In, Bits<16>>

data_outbound: Signal<In, Bits<N>>

data_inbound: Signal<Out, Bits<N>>

start_send: Signal<In, Bit>

transfer_done: Signal<Out, Bit>

continued_transaction: Signal<In, Bit>

busy: Signal<Out, Bit>

wires: SPIWiresMaster

Implementations

impl<const N: usize> SPIMaster<N>

pub fn new(config: SPIConfig) -> Self

Trait Implementations

impl<const N: usize> Block for SPIMaster<N>

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl<const N: usize> Logic for SPIMaster<N>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>