Struct rust_hdl::widgets::sdram::basic_controller::SDRAMBaseController

pub struct SDRAMBaseController<const R: usize, const C: usize, const L: usize, const D: usize> {
    pub clock: Signal<In, Clock>,
    pub sdram: SDRAMDriver<D>,
    pub data_in: Signal<In, Bits<L>>,
    pub write_not_read: Signal<In, Bit>,
    pub cmd_strobe: Signal<In, Bit>,
    pub cmd_address: Signal<In, Bits<32>>,
    pub busy: Signal<Out, Bit>,
    pub data_out: Signal<Out, Bits<L>>,
    pub data_valid: Signal<Out, Bit>,
    pub error: Signal<Out, Bit>,
    /* private fields */
}

Fields

clock: Signal<In, Clock>

sdram: SDRAMDriver<D>

data_in: Signal<In, Bits<L>>

write_not_read: Signal<In, Bit>

cmd_strobe: Signal<In, Bit>

cmd_address: Signal<In, Bits<32>>

busy: Signal<Out, Bit>

data_out: Signal<Out, Bits<L>>

data_valid: Signal<Out, Bit>

error: Signal<Out, Bit>

Implementations

impl<const R: usize, const C: usize, const L: usize, const D: usize> SDRAMBaseController<R, C, L, D>

pub fn new(
    cas_delay: u32,
    timings: MemoryTimings,
    buffer: OutputBuffer
) -> SDRAMBaseController<R, C, L, D>

Trait Implementations

impl<const R: usize, const C: usize, const L: usize, const D: usize> Block for SDRAMBaseController<R, C, L, D>

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl<const R: usize, const C: usize, const L: usize, const D: usize> Logic for SDRAMBaseController<R, C, L, D>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>