Struct rust_hdl::widgets::spi::slave::SPISlave

pub struct SPISlave<const N: usize> {
    pub clock: Signal<In, Clock>,
    pub reset: Signal<In, Reset>,
    pub wires: SPIWiresSlave,
    pub disabled: Signal<In, Bit>,
    pub busy: Signal<Out, Bit>,
    pub data_inbound: Signal<Out, Bits<N>>,
    pub start_send: Signal<In, Bit>,
    pub data_outbound: Signal<In, Bits<N>>,
    pub bits: Signal<In, Bits<16>>,
    pub continued_transaction: Signal<In, Bit>,
    pub transfer_done: Signal<Out, Bit>,
    /* private fields */
}

Fields

clock: Signal<In, Clock>

reset: Signal<In, Reset>

wires: SPIWiresSlave

disabled: Signal<In, Bit>

busy: Signal<Out, Bit>

data_inbound: Signal<Out, Bits<N>>

start_send: Signal<In, Bit>

data_outbound: Signal<In, Bits<N>>

bits: Signal<In, Bits<16>>

continued_transaction: Signal<In, Bit>

transfer_done: Signal<Out, Bit>

Implementations

impl<const N: usize> SPISlave<N>

Here is a table of the SPI setup: CPOL CPHA EDGE ACTION 0 0 R Sample 0 0 F Change 0 1 R Change 0 1 F Sample 1 0 R Change 1 0 F Sample 1 1 R Sample 1 1 F Change

So Sample on Rising edge if CPOL == CPHA Also, CPHA decides if we start in the sample state or in the change state

pub fn new(config: SPIConfig) -> Self

Trait Implementations

impl<const N: usize> Block for SPISlave<N>

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl<const N: usize> Logic for SPISlave<N>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>