Struct rust_hdl::widgets::mac_fir::MultiplyAccumulateSymmetricFiniteImpulseResponseFilter

source · [−]

pub struct MultiplyAccumulateSymmetricFiniteImpulseResponseFilter<const ADDR_BITS: usize> {
    pub data_in: Signal<In, Signed<16>>,
    pub strobe_in: Signal<In, Bit>,
    pub data_out: Signal<Out, Signed<48>>,
    pub strobe_out: Signal<Out, Bit>,
    pub clock: Signal<In, Clock>,
    pub reset: Signal<In, Reset>,
    pub busy: Signal<Out, Bit>,
    /* private fields */
}

Fields

data_in: Signal<In, Signed<16>>strobe_in: Signal<In, Bit>data_out: Signal<Out, Signed<48>>strobe_out: Signal<Out, Bit>clock: Signal<In, Clock>reset: Signal<In, Reset>busy: Signal<Out, Bit>

Implementations

impl<const ADDR_BITS: usize> MultiplyAccumulateSymmetricFiniteImpulseResponseFilter<ADDR_BITS>

pub fn new(coeffs: &[i16 ]) -> Self

Trait Implementations

impl<const ADDR_BITS: usize> Block for MultiplyAccumulateSymmetricFiniteImpulseResponseFilter<ADDR_BITS>

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl<const ADDR_BITS: usize> Logic for MultiplyAccumulateSymmetricFiniteImpulseResponseFilter<ADDR_BITS>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

Auto Trait Implementations

impl<const ADDR_BITS: usize> RefUnwindSafe for MultiplyAccumulateSymmetricFiniteImpulseResponseFilter<ADDR_BITS>

impl<const ADDR_BITS: usize> Send for MultiplyAccumulateSymmetricFiniteImpulseResponseFilter<ADDR_BITS>

impl<const ADDR_BITS: usize> Sync for MultiplyAccumulateSymmetricFiniteImpulseResponseFilter<ADDR_BITS>

impl<const ADDR_BITS: usize> Unpin for MultiplyAccumulateSymmetricFiniteImpulseResponseFilter<ADDR_BITS>

impl<const ADDR_BITS: usize> UnwindSafe for MultiplyAccumulateSymmetricFiniteImpulseResponseFilter<ADDR_BITS>

Blanket Implementations

impl<T> Any for T where
T: 'static + ?Sized,

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