Struct rust_hdl::bsp::ok_core::spi::OKSPIMaster

pub struct OKSPIMaster {
    pub wires: SPIWiresMaster,
    pub ok1: Signal<In, Bits<31>>,
    pub ok2: Signal<Out, Bits<17>>,
    pub clock: Signal<In, Clock>,
    pub reset: Signal<In, Reset>,
    /* private fields */
}

Fields

wires: SPIWiresMaster

ok1: Signal<In, Bits<31>>

ok2: Signal<Out, Bits<17>>

clock: Signal<In, Clock>

reset: Signal<In, Reset>

Implementations

impl OKSPIMaster

pub fn new(config: OKSPIMasterAddressConfig, spi_config: SPIConfig) -> Self

Trait Implementations

impl Block for OKSPIMaster

fn connect_all(&mut self)

fn update_all(&mut self)

fn has_changed(&self) -> bool

fn accept(&self, name: &str, probe: &mut dyn Probe)

impl Logic for OKSPIMaster

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog