Struct Accum 

pub struct Accum<const N: usize, const M: usize, const P: usize> {
    pub clock: Signal<In, Clock>,
    pub strobe_in: Signal<In, Bit>,
    pub data_in: Signal<In, Bits<N>>,
    pub strobe_out: Signal<Out, Bit>,
    pub data_out: Signal<Out, Bits<M>>,
    /* private fields */
}

Fields

clock: Signal<In, Clock>

strobe_in: Signal<In, Bit>

data_in: Signal<In, Bits<N>>

strobe_out: Signal<Out, Bit>

data_out: Signal<Out, Bits<M>>

Implementations

impl<const N: usize, const M: usize, const P: usize> Accum<N, M, P>

pub fn new(count: usize) -> Self

Trait Implementations

impl<const N: usize, const M: usize, const P: usize> Block for Accum<N, M, P>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<const N: usize, const M: usize, const P: usize> Clone for Accum<N, M, P>

fn clone(&self) -> Accum<N, M, P>

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl<const N: usize, const M: usize, const P: usize> Debug for Accum<N, M, P>

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<const N: usize, const M: usize, const P: usize> Logic for Accum<N, M, P>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>