Struct AsynchronousFIFO 

pub struct AsynchronousFIFO<D: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> {

    pub read: Signal<In, Bit>,
    pub data_out: Signal<Out, D>,
    pub empty: Signal<Out, Bit>,
    pub almost_empty: Signal<Out, Bit>,
    pub underflow: Signal<Out, Bit>,
    pub read_clock: Signal<In, Clock>,
    pub read_fill: Signal<Out, Bits<NP1>>,
    pub write: Signal<In, Bit>,
    pub data_in: Signal<In, D>,
    pub full: Signal<Out, Bit>,
    pub almost_full: Signal<Out, Bit>,
    pub overflow: Signal<Out, Bit>,
    pub write_clock: Signal<In, Clock>,
    pub write_fill: Signal<Out, Bits<NP1>>,
    /* private fields */
}

Fields

read: Signal<In, Bit>

data_out: Signal<Out, D>

empty: Signal<Out, Bit>

almost_empty: Signal<Out, Bit>

underflow: Signal<Out, Bit>

read_clock: Signal<In, Clock>

read_fill: Signal<Out, Bits<NP1>>

write: Signal<In, Bit>

data_in: Signal<In, D>

full: Signal<Out, Bit>

almost_full: Signal<Out, Bit>

overflow: Signal<Out, Bit>

write_clock: Signal<In, Clock>

write_fill: Signal<Out, Bits<NP1>>

Trait Implementations

impl<D: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Block for AsynchronousFIFO<D, N, NP1, BLOCK_SIZE>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<D: Default + Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Default for AsynchronousFIFO<D, N, NP1, BLOCK_SIZE>

fn default() -> AsynchronousFIFO<D, N, NP1, BLOCK_SIZE>

Returns the “default value” for a type.

impl<D: Synth, const N: usize, const NP1: usize, const BLOCK_SIZE: u32> Logic for AsynchronousFIFO<D, N, NP1, BLOCK_SIZE>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>