Struct RAM

pub struct RAM<D: Synth, const N: usize> {
    pub read_address: Signal<In, Bits<N>>,
    pub read_clock: Signal<In, Clock>,
    pub read_data: Signal<Out, D>,
    pub write_address: Signal<In, Bits<N>>,
    pub write_clock: Signal<In, Clock>,
    pub write_data: Signal<In, D>,
    pub write_enable: Signal<In, bool>,
    /* private fields */
}

Fields

read_address: Signal<In, Bits<N>>

read_clock: Signal<In, Clock>

read_data: Signal<Out, D>

write_address: Signal<In, Bits<N>>

write_clock: Signal<In, Clock>

write_data: Signal<In, D>

write_enable: Signal<In, bool>

Implementations

impl<D: Synth, const N: usize> RAM<D, N>

pub fn new(values: BTreeMap<Bits<N>, D>) -> Self

Trait Implementations

impl<D: Synth, const N: usize> Block for RAM<D, N>

fn connect_all(&mut self)

Connects the internal signals of the circuit - used to initialize the circuit

fn update_all(&mut self)

Propogate changes from inputs to outputs within the circuit

fn has_changed(&self) -> bool

Returns true if anything in the circuit has changed (outputs or internal state)

fn accept(&self, name: &str, probe: &mut dyn Probe)

The visitor pattern - allows a circuit to be probed by a Probe struct.

impl<D: Default + Synth, const N: usize> Default for RAM<D, N>

fn default() -> RAM<D, N>

Returns the “default value” for a type.

impl<I: Iterator<Item = D>, D: Synth, const N: usize> From<I> for RAM<D, N>

fn from(v: I) -> Self

Converts to this type from the input type.

impl<D: Synth, const N: usize> Logic for RAM<D, N>

fn update(&mut self)

fn connect(&mut self)

fn hdl(&self) -> Verilog

fn timing(&self) -> Vec<TimingInfo>